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Rev.2.1 Nov.14, 2019

AX6901/2/3/4

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FUNCTION DESCRIPTIONS

A microprocessor’s (µP’s) reset input starts the µP in a known state. The

AX6901/2/3/4 asserts reset to prevent code-execution errors during power-up, power-down,

or brownout conditions. They assert a reset signal whenever the VCC supply voltage

declines below a preset threshold, keeping it asserted for at least 200ms after VCC has

risen above the reset threshold. The AX6901/2/3/4 has a push-pull output stage.

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APPLICATION INFORMATION

Negative-Going VCC Transients

In addition to issuing a reset to the µP during power-up, power-down, and brownout

conditions, the AX6901/2/3/4 is relatively immune to short-duration negative-going VCC

transients (glitches).

The AX6901/2/3/4 does not generate a reset pulse. The graph was generated using a

negative going pulse applied to VCC, starting 0.5V above the actual reset threshold and

ending below it by the magnitude indicated (reset comparator overdrive). The graph

indicates the maximum pulse width a negative going VCC transient can have without

causing a reset pulse. As the magnitude of the transient increases (goes farther below the

reset threshold), the maximum allowable pulse width decreases. Typically, a VCC transient

that goes 50mV below the reset threshold A 0.1µF bypass capacitor mounted as close as

possible to the VCC pin provides additional transient immunity.

Ensuring a Valid Reset Output Down to VCC = 0

RESET

is guaranteed to be a logic low for VCC > 1.0V. Once VCC exceeds the reset

threshold, an internal timer keepsRESET low for the reset timeout period; after this interval,

RESET

goes high. If a brownout condition occurs (VCC dips below the reset threshold),

RESET

goes low. Any time VCC goes below the reset threshold, the internal timer resets

to zero, and RESET goes low. The internal timer starts after VCC returns above the reset

threshold, and RESET remains low for the reset timeout period.

When VCC falls below 1.0V, theAX6901/3 RESET output no longer sinks current—it

becomes an open circuit. Therefore, high-impedance CMOS logic inputs connected

toRESETcan drift to undetermined voltages.

This presents no problem in most applications since most µP and other circuitry is

inoperative with VCC below 1.0V. However, in applications where RESET must be valid

down to 0V, adding a pull down resistor to RESET causes any stray leakage currents to flow

to ground, holding RESET low. R1’s value is not critical; 100k is large enough not to load

RESET

and small enough to pull RESET to ground. For theAX6902/4 if RESET is

required to remain valid for VCC < 1.0V.