Two’s Complement, Dual 12-Bit DAC

AD5329

REV PrC 20 DEC 99

– 3 –

Information contained in this Preliminary Data Sheet describes a product in the early definition stage. There is no guarantee that the information contained here will become a final product in its present

form. For latest information contact Walt Heinzer/Analog Devices, Santa Clara, CA. TEL 408 562-7254; FAX 408 562-7154; email; walt.heinzer@analog.com

otherwise noted)

Operating Temperature Range.......................... 0°C to +70°C

Storage Temperature ................................... -65°C to +150°C

Lead Temperature (Soldering, 10 sec) ....................... +300°C

Thermal Resistance

θ

JA,

AD5329 Two’s Complement Coding

Binary

Hexadecimal

Scale

0111 1111 1111

7 F F

+FS

0111 1111 1110

7 F F

+FS-1LSB

0000 0000 0001

0 0 1

BZS+1LSB

0000 0000 0000

0 0 0

BZS

1111 1111 1111

F F F

BZS-1LSB

1000 0000 0001

8 0 1

-FS+1LSB

1000 0000 0000

8 0 0

-FS

TABLE 2: AD5329 PIN Descriptions

Pin

Name

Description

1

Positive power supply, specified for operation

at +5V.

2

SDA

Serial Data Input, MSB first format

3

NC

No Connect

4

DAC B Voltage Output (A0 = logic “1”)

5

DAC A Voltage Output (A0 = logic “0”)

6

Virtual Bipolar Zero (Active Output)

7

NC

No Connect

8

FSYNC

Frame Sync Input, Active Low. When

FSYNC

returns HIGH data in the serial input register

is transferred into the DAC register.

9

SCLK

Serial Clock Input, positive edge triggered

10

GND

Ground

TABLE 1: AD5329 Serial-Data Word Format

ADDR

DATA

B16 B15 B14 B13 B12 B11

<>

B4

B3

B2

B1

A0

X

SD

0

D11 D10

<>

D3

D2

D1

D0

MSB

LSB

SD: Shutdown is active high B14="1". Both DACs and the DACREF

becomes open circuit.

SDI

AD5329

1

0

1

SCLK

0

1

FSYNC

0

A0

X

SD

0

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

Figure 1A. Timing Diagram