MAX20804

4A, 3MHz, 2.7V to 16V, Step-Down Switching

Regulator

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Internal Linear Regulator

The device contains an internal 1.8V linear regulator (LDO). The 1.8V LDO output voltage on VCC is derived from the

VDDH pin by default.

The 1.8V voltage on the VCC pin supplies the current to the MOSFET drivers. A decoupling capacitor of at least 2.2μF

must be connected between VCC and AGND.

Startup and Shutdown

The startup and shutdown timing is shown in Figure 3. When the VCC pin voltage is above its rising UVLO threshold, the

device goes through an initialization procedure. Configuration settings on the PGM_ pins are read. Once initialization is

complete, the device detects the VDDH UVLO and EN statuses. When both are above their rising thresholds, the soft-

start begins and switching is enabled. The output voltage starts to ramp up. The soft-start ramp time is 3ms. If there are

no faults, the open-drain PGOOD pin is released from being held low after the soft-start ramp is complete. The device

supports smooth startup with the output prebiased.

During operation, if either the VDDH UVLO or EN falls below its threshold, switching is stopped immediately. The output

voltage is discharged by the load current.

VDDH

VOUT

(PREBIASED)

INTERNA L

SOFT-START RAMP

LX

VCC

EN

tINIT

tEN_RISING_DELAY

tEN_FALLING_DELAY

tSS

PGOOD

tINIT = 800µs

tEN_RISING_DELAY = 250µs

tSS = 3ms

tEN_FALLING_DELAY = 2µs

Figure 3. Startup and Shutdown Timing

Fault Handling

Input Undervoltage Lockout (VDDH UVLO)

The MAX20804 internally monitors the VDDH voltage level. When the input supply voltage is below the UVLO threshold,

the device stops switching and drives the PGOOD pin low. The device restarts after 20ms if the UVLO status is cleared.

See the Startup and Shutdown section for the start-up sequence.