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Data Sheet

LTC9105

APPLICATIONS INFORMATION

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Rev. A | 19 of 22

EXTERNAL COMPONENT SELECTION

PoE Input Bridge

A PD is required to polarity-correct its input voltage. There are sev-

eral different options available for bridge rectifiers; silicon diodes,

Schottky diodes, and ideal diodes. When silicon or Schottky diode

bridges are used, the diode forward voltage drops affect the voltage

at the VIN pin. The LTC9105 is designed to tolerate these voltage

drops. Note, the parameters shown in Electrical Characteristics are

specified at the LTC9105 package pins.

A silicon diode bridge consumes up to 4% of the available power. In

addition, silicon diode bridges exhibit poor pairset-to-pairset unbal-

ance performance. Each branch of a silicon diode bridge shares

source/return current, and thermal runaway can cause large, non-

compliant current unbalances between pairsets.

While using Schottky diodes can help reduce the power loss with a

lower forward voltage, the Schottky bridge may not be suitable for

high temperature PD applications. Schottky diode bridges exhibit

temperature induced leakage currents. The leakage current has a

voltage dependency that can invalidate the measured detection sig-

nature. In addition, these leakage currents can back-feed through

the unpowered branch and the unused bridge, violating IEEE 802.3

specifications.

For high efficiency applications, the LT9105 supports an LT4321-

based PoE ideal diode bridge that reduces the forward voltage

drop from 0.7V to 20mV per diode while maintaining IEEE 802.3

compliance. The LT4321 simplifies thermal design, eliminates costly

heat sinks, and can operate in space-constrained applications. In

addition, with the very low voltage drop of the LT4321 ideal diode

bridge, the LTC9105's voltage readback is closer to the PD's true

input voltage.

Input Capacitor

A 0.1μF capacitor is needed from VIN to SNSN to meet the input

impedance requirement in IEEE 802.3 and to properly bypass the

LTC9105. When operating with the LT4321, locally bypass each

with a 0.047μF capacitor, thus keeping the total port capacitance

within specification. Place each capacitor as close as possible to

both the LTC9105 and LT4321. See Figure 26.

Transient Voltage Suppressor

The LTC9105 specifies an absolute maximum voltage of 100V and

is designed to tolerate brief over voltage events due to Ethernet

cable surges. To protect the LTC9105 from an overvoltage event,

install a unidirectional transient voltage suppressor (TVS) such as

an SMAJ58A or PTVS58VP1UTP between the VIN and SNSN pins.

Place the TVS as close as possible to the LTC9105.

Exposed Pad

The LTC9105 package has an exposed pad internally connected

to RTN. The exposed pad may only be connected to RTN on the

printed circuit board. Ensure the Exposed Pad has access to a

printed circuit board plane as a heat sink.

Signature Resistor (RSIG)

A 24.9kΩ, 1% resistor must be connected between VIN and RSIG

for IEEE compliant detection. The RSIG pin is low impedance

when the input voltage is in the VSIG range, then switches to high

impedance as the input voltage crosses into the VCLASS range to

save power. The RSIG pin becomes low impedance again when the

input voltage falls below VRESET.

External MOSFET

Careful selection of the power MOSFET is critical to system reliabil-

ity. Choosing a MOSFET requires extensive analysis and testing of

the MOSFET SOA curve against the various PD current limit condi-

tions. Analog Devices recommends the PSMN075-100MSE for PDs

configured to deliver up to 51W maximum port power (single-signa-

ture) or 25.5W maximum pairset power (dual-signature). For PDs

configured to power up to 71.3W maximum port power (single-sig-

nature) or 35.6W maximum pairset power (dual-signature), Analog

Devices recommends the PSMN040-100MSE. These MOSFETs

are selected for their proven reliability in PoE applications. Contact

Analog Devices before using a MOSFET other than one of these

recommended parts.

I2C Interface Isolation

A high speed isolation interface is recommended for I2C commu-

nications with the LTC9105. Analog Devices recommends the AD-

uM1252ASA for I2C isolation.

Figure 23 shows the suggested connection of the I2C interface

when the system processor is powered by an isolated supply.

Figure 23. I2C Interface Isolation

Pull-up resistors connected to the isolator should be adjusted based

on the specific isolator and the desired speed of the I2C interface.

LAYOUT CONSIDERATIONS

Sense Resistor

The LTC9105 is designed for a low 50mΩ current sense resistance.

For the LTC9105 ADC to present an accurate current telemetry, the

sense resistors should have ±1% tolerance or better and no more

than ±200ppm/°C temperature coefficient.

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