TMP86FS49AIUG datasheet(60/296 Pages) TOSHIBA

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Page 44

3. Interrupt Control Circuit

3.7 External Interrupts

TMP86FS49AIUG

Note 1: fc: High-frequency clock [Hz], *: Don’t care

Note 2: When the system clock frequency is switched between high and low or when the external interrupt control register

(EINTCR) is overwritten, the noise canceller may not operate normally. It is recommended that external interrupts are dis-

abled using the interrupt enable register (EIR).

Note 3: The maximum time from modifying INT1NC until a noise reject time is changed is 26/fc.

External Interrupt Control Register

EINTCR

5432

(0037H)

INT1NC

INT0EN

INT3ES

INT2ES

INT1ES

(Initial value: 00** 000*)

INT1NC

Noise reject time select

0: Pulses of less than 63/fc [s] are eliminated as noise

1: Pulses of less than 15/fc [s] are eliminated as noise

R/W

INT0EN

P00/INT0 pin configuration

0: P00 input/output port

1: INT0 pin (Port P00 should be set to an input mode)

R/W

INT3 ES

INT3 edge select

0: Rising edge

1: Falling edge

R/W

INT2 ES

INT2 edge select

0: Rising edge

1: Falling edge

R/W

INT1 ES

INT1 edge select

0: Rising edge

1: Falling edge

R/W

TMP86FS49AIUG Datasheet(PDF) 60 Page - Toshiba Semiconductor

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