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ETA1661FSG Datasheet(PDF) 6 Page - ETA SOLUTIONS CO. LIMITED |
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ETA1661FSG Datasheet(HTML) 6 Page - ETA SOLUTIONS CO. LIMITED |
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6 / 8 page ![]() ETA1661 www.etasolution.com 6 Empowering Thinkers FEATURE DESCRIPTION The ETA1661 is a synchronous buck regulator ICs that integrates the adaptive COT control, top and bottom switches on the same die to minimize the switching transition loss and conduction loss. ETA1661 is a wide input range, high-efficiency and high frequency DC-to-DC step-down switching regulator, capable of delivering up to 4A of output current. It adopts an Adaptive COT control scheme that enables very fast transient response and provides a very smooth transition when the output varies from light load to heavy load. It compares the sum of the FB voltage and a ripple voltage that mimics the voltage due to the output ESR and capacitance. The constant-on-time timer varies with line to achieve relative constant switching frequency across line. Light Load Operation Traditionally, a fixed constant frequency PWM DC-DC regulator always switches even when the output load is small. When energy is shuffling back and forth through the power MOSFET, power is lost due to the finite Rdson of the MOSFET and parasitic capacitances. At light load, this loss is prominent and efficiency is therefore very low. ETA1661 goes into a power save mode during light load, thereby extending the range of high efficiency operation. Enable EN is a digital control pin that turns the ETA1661 on and off. Drive EN High to turn on the regulator, drive it Low to turn it off. An internal 1MΩ resistor from EN pin to GND allows EN to float to shut down the chip. Connecting the EN pin through a pull up resistor or shorted EN to IN will automatically turn on the chip whenever plug in IN. Over Current Protection and Hiccup ETA1661 has a cycle-by-cycle over current limit for both inductor current peak value and inductor current valley value. Meanwhile both inductor currents during LS_FET ON or HS_FET ON are monitored. During LS_FET on, sensed inductor current is monitored by a valley current limit comparator. HS_FET always wait until valley current limit disappear to be on again. Once, HS_FET is ON, it will be immediately OFF whenever max on time or peak current limit is reached. When the output voltage drop until FB falls below UV threshold (70% Vnormal), the ETA1661 will enter hiccup mode. It will turn off the chip immediately for 6mS. After that, it will try to re-starts as normal for 2ms. After 2ms, if FB is still below UV threshold, then the chip enters hiccup mode again. If FB is higher than UV threshold, it will enter the normal mode. Over-Temperature Protection Thermal protection disables the output when the junction temperature rises to approximately 150°C, allowing the device to cool down. When the junction temperature cools down approximately 110°C, the output circuitry |
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