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TC74ACT112FN Datasheet(PDF) 4 Page - Toshiba Semiconductor

Part # TC74ACT112FN
Description  CMOS Digital Integrated Circuit Silicon Monolithic Dual J-K Flip Flop with Preset and Clear
PDF  9 Pages
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Manufacturer  TOSHIBA [Toshiba Semiconductor]
Direct Link  http://www.semicon.toshiba.co.jp/eng
Logo TOSHIBA - Toshiba Semiconductor

TC74ACT112FN Datasheet(HTML) 4 Page - Toshiba Semiconductor

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TC74ACT112P/F/FN
2007-10-01
4
Electrical Characteristics
DC Characteristics
Test Condition
Ta
= 25°C
Ta
= −40 to
85°C
Characteristics
Symbol
VCC
(V)
Min
Typ.
Max
Min
Max
Unit
High-level input
voltage
VIH
⎯
4.5 to
5.5
2.0
⎯
⎯
2.0
⎯
V
Low-level input
voltage
VIL
⎯
4.5 to
5.5
⎯
⎯
0.8
⎯
0.8
V
High-level output
voltage
VOH
VIN
= VIH or
VIL
IOH = −50 μA
IOH = −24 mA
IOH = −75 mA
(Note)
4.5
4.5
5.5
4.4
3.94
⎯
4.5
⎯
⎯
⎯
⎯
⎯
4.4
3.80
3.85
⎯
⎯
⎯
V
Low-level output
voltage
VOL
VIN
= VIH or
VIL
IOL = 50 μA
IOL = 24 mA
IOL = 75 mA
(Note)
4.5
4.5
5.5
⎯
⎯
⎯
0.0
⎯
⎯
0.1
0.36
⎯
⎯
⎯
⎯
0.1
0.44
1.65
V
Input leakage
current
IIN
VIN = VCC or GND
5.5
⎯
⎯
±0.1
⎯
±1.0
μA
ICC
VIN = VCC or GND
5.5
⎯
⎯
4.0
⎯
40.0
μA
Quiescent supply
current
IC
Per input: VIN = 3.4 V
Other input: VCC or GND
5.5
⎯
⎯
1.35
⎯
1.5
mA
Note:
This spec indicates the capability of driving 50
Ω transmission lines.
One output should be tested at a time for a 10 ms maximum duration.
Timing Requirements (input: tr = tf = 3 ns)
Test Condition
Ta
=
25°C
Ta
=
−40 to
85°C
Characteristics
Symbol
VCC (V)
Limit
Limit
Unit
Minimum pulse width
(
CK )
tW (L)
tW (H)
⎯
5.0
± 0.5
5.0
5.0
ns
Minimum pulse width
( CLR , PR )
tW (L)
⎯
5.0
± 0.5
5.0
5.0
ns
Minimum set-up time
ts
⎯
5.0
± 0.5
5.0
5.0
ns
Minimum hold time
th
⎯
5.0
± 0.5
1.0
1.0
ns
Minimum removal time
( CLR , PR )
trem
⎯
5.0
± 0.5
3.0
3.0
ns



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