AD8488

Data Sheet

Rev. A | Page 14 of 20

TIMING SIGNALS

Figure 17 is the gate line timing diagram. The gate line sequence

requires 405 clock cycles for channel integration and the sequential

transfer to an ADC. The timing signals, IRST, GRST, and HOLD,

control the integration, gain, and hold switches, respectively, and

define the timing intervals required by each of the integrator

channels. These signals may be generated by an FPGA, ROM,

or similar device.

The balance of the signals shown in Figure 16 are user discretionary

and encoded according to Table 8 through Table 11 for select gain,

hold capacitor values, low-pass filter values, and mux output channels

for troubleshooting.

Timing Notes

Refer to Figure 17 and the following timing notes:

1. The CLK frequency can range from 1 MHz to 15 MHz.

2. RST must be low (active) for the first half clock of the gate

line cycle.

3. tGRST must be ≥ 6.1 µs.

4. tINT must be ≥ 12 µs.

5. The CK_ENa and CK_ENb intervals must be exactly 67

clocks. The time can be longer if tCLK exceeds 67 ns.

6. The tIRST interval must be exactly 130 CLKs.

RST

tDELAY3 (SEE NOTE 3)

tDELAY3 (SEE NOTE 3)

67 CLKS

tDELAY2 (SEE NOTE2)

67 CLKS

tCLK (SEE NOTE 1)

tDELAY2 (SEE NOTE 2)

NOTES

1. IN THIS EXAMPLE

tCLK = 67ns (15MHz).

2. ¼ CLK <

tDELAY2 < ½ CLK.

3. 0 CLK <

tDELAY3 < ¼ CLK.

4.

tGATE = tGRST + tINT + tREAD = 27µs.

5. ALL LOGIC LEVELS EXCEPT RST ARE ACTIVE HIGH.

6. SHOWN AS ACTIVE HIGH – CHARGE IS TRANSFERRED TO ALL CHANNELS DURING THIS INTERVAL.

IRST

GRST

HOLD

CLK

CK_ENa

GATED CLKa

CK_ENb

GATED CLKb

TFT_GATE

(SEE NOTE 5)

tINT (12µs)

≥6µs

tCLK (SEE NOTE 1) ≥ 67ns

1 GATE LINE:

tGATE (27ms) (WITH 15MHz CLOCK; SEE NOTE 4)

18.1µs

tREAD (133 CLKS)

tIRST (130 CLKS)

tGRST ≥ 6.1µs

Figure 17. Gate Line Timing Diagram