SML2108F datasheet(8/21 Pages) SUMMIT

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SML2108

2053 2.2 11/07/00

SUMMIT MICROELECTRONICS, Inc.

PRELIMINARY

Figure 2. Output Block 1: Mean Power Control

Figure 3. Output Block 2: I

MOD

The built-in integration time constant is nominally 1ms.

This is accomplished by using an internal 2M

Ω resistor

and 500pF capacitor. The time constant can be modified

by adding external capacitance between the CAP1 and

CAP2 terminals, and/or by adding external resistance

between the DETECT and CAP1 terminals. For stability

reasons it is not recommended that the time constant be

decreased to less than 100us.

The output of an internal 10-Bit DAC biases the positive

terminal of the integrating amplifier. This DAC provides an

analog reference to the integrator which is useful for initial

calibration of the laser module. The full-scale value of the

DAC output is 1.5V.

10-Bit Bias Control D/A

The 10-Bit D/A determines the reference voltage of the

non-inverting terminal of the integrating amplifier in the

mean power control loop. Associated with this DAC are a

10-Bit volatile register and a 10-Bit nonvolatile (NV) regis-

ter. The content of the volatile register determines the

DAC output voltage. The DAC output voltage is given by

the following relation:

1.5V

1024

=×

where X = the decimal equivalent of the 10-Bit data stored

in the volatile register. Note that the DAC output voltage

is not directly accessible external to the chip. However,

when the SML2108 is placed in a typical application circuit,

the mean power control feedback loop forces the voltage

at the DETECT pin to be the same as the DAC output. On

device power-up the volatile register may be loaded with

all zeroes, or it may be loaded from the contents of the 10-

Bit nonvolatile register.

Access to the 10-Bit volatile register is obtained via the 2-

wire interface at slave address 1001BIN, word address 0.

Refer to Figures 9, 10, 12, and 13 for details on program-

ming and reading data from the 10-Bit register. When

writing to the volatile register the new DAC output will

become valid immediately at the end of the write com-

mand. Reading the volatile register has no effect on the

DAC output. Reading or writing the volatile register has no

effect on the contents of the nonvolatile register.

The 10-Bit NV register can only be accessed indirectly

through the volatile register. The command sequence to

communicate with the NV register is the same as that of

VDD

BIAS

CONTROL

ADC

Input

BIASP

BIASN

IBIAS Sink

0 to 100 mA

IBIAS Source

0 to 10 mA or

0 to 100 mA

From MPC

Integrator

2053 Fig02

VDD

MOD

CONTROL

MODP

MODN

IMOD Sink

0 to 100 mA

IMOD Source

0 to 10 mA or

0 to 100 mA

From IMOD

DAC

2053 Fig03

the volatile register, except word address 2 is used instead

of 0. When reading the NV register, the data is first

transferred into the volatile register where it may be

accessed by the serial interface. Note that upon this

transfer the DAC output will change immediately to reflect

the new data. Similarly, when writing to the NV register,

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