Data Sheet Rev. G, January 2020 | Subject to change without notice

29 of 46

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ACT8945A

Advanced PMU for Atmel SAMA5Dx Series & SAM9 Series Processors

Push-Button Control

The ACT8945A is designed to initiate a system enable

sequence when the nPBIN multi-function input is

asserted. Once this occurs, a power-on sequence

commences, as described below. The power-on

sequence must complete and the microprocessor must

take control (by asserting PWRHLD) before nPBIN is

de-asserted. If the microprocessor is unable to

complete its power-up routine successfully before the

user

releases

the

push-button,

the

ACT8945A

automatically shuts the system down. This provides

protection against accidental or momentary assertions

of the push- button. If desired, longer “push-and-hold”

times can be implemented by simply adding an

additional time delay before asserting PWRHLD.

Control Sequences

The ACT8945A features a variety of control sequences

that are optimized for supporting system enable and

disable sequences of Atmel SAMA5D2 and SAMA5D3

series and SAM9 series application processors.

Enabling/Disabling Sequence

ACT8945AQJ305 Sequence

A typical enable sequence is initiated whenever the

following conditions occurs:

1) nPBIN is asserted low via 50KΩ resistance, or

2) A valid input voltage is present at CHGIN.

The enable sequence begins by enabling REG3/REG5.

When REG3/REG5 reaches its power-OK threshold,

nRSTO is asserted low, resetting the microprocessor.

When REG3/REG5 reaches its power-OK threshold for

2ms, REG1 is enabled. When REG3/REG5 reaches its

power-OK threshold for 4ms, REG2 is enabled. When

REG3/REG5 reaches its power-OK threshold for 8ms,

REG4 is enabled. When REG3 is above its power-OK

threshold when the reset timer expires, nRSTO is de-

asserted, allowing the microprocessor to begin its boot

sequence. REG6 and REG7 can be enabled or disabled

by PWREN after system powers up.

During the boot sequence, the microprocessor must

assert PWRHLD, holding the regulators to ensure that

the system remains powered after nPBIN is released.

As with the enable sequence, a typical disable

sequence is initiated when the user presses the push-

button, which interrupts the processor via the nPBSTAT

output. The actual disable sequence is completely

software-controlled, but typically involved initiating

various

“clean-up”

processes

before

finally

set

MSTROFF[ ] bit to 1 to shut the system down.

Figure 3:

ACT8945AQJ305-T Enable/Disable Sequence

: Typical value shown, actual delay time may vary from (T-1ms) x 88% to T x 112%, where T is the typical delay time setting.