ST10F272M datasheet(23/175 Pages) STMICROELECTRONICS

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ST10F272M

Memory organization

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accesses are possible). Two waitstates give an access time of 100ns at 40 MHz CPU clock.

No tristate waitstate is used.

X-Miscellaneous: Address range 00’EB00h - 00’EBFFh is reserved for the access to a set

of XBUS additional features. They are enabled by setting XPEN bit 2 of the SYSCON

demultiplexed addresses and a 16-bit data bus (only word accesses are possible). Two

waitstates give an access time of 100ns at 40 MHz CPU clock. No tristate waitstate is used.

The following set of features are provided:

●

CLKOUT programmable divider

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XBUS interrupt management registers

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ADC multiplexing on P1L register

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Port1L digital disable register for extra ADC channels

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CAN2 multiplexing on P4.5/P4.6

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CAN1-2 main clock prescaler

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Main Voltage Regulator disable for power-down mode

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TTL / CMOS threshold selection for Port0, Port1, and Port5

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Flash Temporary Unprotection

In order to meet the needs of designs where more memory is required than is provided on

chip, up to 16 Mbytes of external memory can be connected to the microcontroller.

Visibility of XBUS peripherals

In order to keep the ST10F272M compatible with the ST10F168 / ST10F269, the XBUS

peripherals can be selected to be visible on the external address / data bus. Different bits for

X-Peripheral enabling in XPERCON register must be set. If these bits are cleared before the

global enabling with XPEN bit in SYSCON register, the corresponding address space, port

pins and interrupts are not occupied by the peripherals, thus the peripheral is not visible and

not available. Refer to Chapter 23: Register set on page 108.

XPERCON and X-Peripheral clock gating

As already mentioned, the XPERCON register must be programmed to enable the single

XBus modules separately. The XPERCON is a read/write ESFR register.

The new feature of Clock Gating has been implemented by means of this register: Once the

EINIT instruction has been executed, all the peripherals (except RAMs and XMISC) not

enabled in the XPERCON register are not be clocked. The clock gating can reduce power

consumption and improve EMI when the user doesn’t use all X-Peripherals.

Note:

When the clock has been gated in the disabled Peripherals, no Reset will be raised once the

EINIT instruction has been executed.

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