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ST7LITE0XY0 Datasheet(PDF) 44 Page - STMicroelectronics |
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ST7LITE0XY0 Datasheet(HTML) 44 Page - STMicroelectronics |
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44 / 124 page  ST7LITE0xY0, ST7LITESxY0 44/124 I/O PORTS (Cont’d) Figure 29. I/O Port General Block Diagram Table 9. I/O Port Mode Options Legend: NI - not implemented Off - implemented not activated On - implemented and activated Configuration Mode Pull-Up P-Buffer Diodes to VDD to VSS Input Floating with/without Interrupt Off Off On On Pull-up with/without Interrupt On Output Push-pull Off On Open Drain (logic level) Off DR DDR OR PAD VDD ALTERNATE ENABLE ALTERNATE OUTPUT 1 0 OR SEL DDR SEL DR SEL PULL-UP CONDITION P-BUFFER (see table below) N-BUFFER PULL-UP (see table below) 1 0 ANALOG INPUT If implemented ALTERNATE INPUT VDD DIODES (see table below) FROM OTHER BITS EXTERNAL SOURCE (eix) INTERRUPT POLARITY SELECTION CMOS SCHMITT TRIGGER REGISTER ACCESS 1 |
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