ADBMS6821 datasheet(20/28 Pages) AD

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Data Sheet

ADBMS6821/ADBMS6822

THEORY OF OPERATION

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to the ready state to cause the XCVRMD pin state to be detected.

For more information, see the Idle Mode and Wake-Up Detection

section.

Table 21. XCVRMD Pin Transceiver Modes

Description

XCVRMD Pin Connection

Standard Bidirectional isoSPI

GND

Standard Bidirectional isoSPI with LPCM Timeout

Monitor Support

20 kΩ resistor to GND

4 Mbps Unidirectional

100 kΩ resistor to GND

2 Mbps with 1-Bit Latency

VDDS

Standard Bidirectional isoSPI

This is the normal communication mode. When the transceiver is

configured in controller mode, it can send and receive communica-

tion at up to 2 Mbps when communicating with ADBMS devices

that support 2 Mbps communication. Otherwise, the transceiver can

send and receive communication at up to 1 Mbps when configured

in either controller or peripheral mode.

Standard Bidirectional isoSPI with LPCM

Timeout Monitor Support

In this mode, when the transceiver is configured in controller mode,

it behaves the same as the standard bidirectional isoSPI mode.

When the transceiver is configured in peripheral mode, it can

receive communication at 2 Mbps, but it does not transmit any

data back to the isoSPI port. The transceiver still receives the data

and decodes it onto the SPI port. When in peripheral mode, the

LPCM feature is enabled, and the device transitions to the listen

state while waiting for heartbeat messages to set the INTR pin

appropriately.

4 Mbps Unidirectional

In this mode, when the transceiver is configured in controller mode,

it can send isoSPI data at up to 4 Mbps. The transceiver does

not receive nor decode isoSPI data when configured in controller

mode. When the transceiver is configured in peripheral mode, it

can receive and decode isoSPI data at up to 4 Mbps. It does not

transmit isoSPI data when configured in peripheral mode.

2 Mbps with 1-Bit Latency

In this mode, the peripheral can operate at 2 Mbps. To achieve

the 2 Mbps rate, the transceiver configured in peripheral mode

transmits the data back from the latching edge of its clock (SCK)

instead of the nonlatching edge. Also, it does not send back data

after receiving a long CS −1 pulse that causes its CS to transition to

logic low.

ISOSPI STATE DIAGRAM

Figure 38 shows the state diagram for isoSPI communications. Dur-

ing periods of no communication, a low-current idle state reduces

power. In the idle state, the ADBMS6821/ADBMS6822 transceivers

shut down most of the circuitry.

In the ready state, all circuitry is enabled and ready to transmit or

receive, but there is no active data transmission on IP and IM.

Supply current increases when actively communicating. Thus, this

condition is referred to as the active state.

Figure 38. isoSPI State Diagram

POWER SUPPLIES

The ADBMS6821/ADBMS6822 transceivers have three power sup-

plies: VDDS, VDD, and VP. VDDS powers the SPI. Connect VDDS

to the same power supply as the SPI to which the SPI bus is

connected. In many cases, that supply is the interface power supply

of a microcontroller. The SPI can operate across the VDDS range of

1.7 V to 5.5 V.

VDDS also supports functions on the MSTR, PHAPOL, and

XCVRMD pins. When VDDS is powered down, the transceiver is

set to peripheral mode. The states of the PHAPOL and XCVRMD

configurations are maintained from the last VDDS power-up.

VDD powers the isoSPI. When actively communicating over isoSPI,

VDD must be in the range of 3 V to 5.5 V. Put a bypass capacitor

of at least 1 µF as close as possible to the VDD pin to maintain

reliable isoSPI communication.

VP powers portions of the transceiver when in LPCM timeout

monitor mode, which allows both VDDS and VDD to be powered

down while maintaining LPCM timeout monitor functionality. VP can

be connected directly to 12 V battery power. If VDD is powered

down, VP must be >6 V to function in LPCM timeout monitor mode.

If high voltage LPCM power is not required, connect VP to VDD.

In this configuration, LPCM timeout monitor mode works over the

whole VDD range.

SUPPLY CURRENT

Table 22 provides equations for estimating IVDD/VP in each state.

The results are for average supply current (as opposed to peak

currents), and assume that a peripheral is returning an equal

number of 0s and 1s. A transceiver configured as a peripheral does

not generate +1 data pulses. Therefore, the average driver current

is less than a transceiver configured as a controller.

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