HM-6514/883

FN2996 Rev.1.00

Page 4 of 9

March 1997

TABLE 2. HM-6514/883 AC ELECTRICAL PERFORMANCE SPECIFICATIONS

Device Guaranteed and 100% Tested

PARAMETER

SYMBOL

(NOTES 1, 2)

CONDITIONS

GROUP

A SUB-

GROUPS

TEMPERA-

TURE

LIMITS

UNITS

HM-6514S/883

HM-6514B/883

HM-6514/883

MIN

MAX

MIN

MAX

MIN

MAX

Chip Enable

Access Time

(1) TELQV

VCC = 4.5 and

5.5V

9, 10, 11

-55oC

 TA

 +125oC

-120

-200

-300

ns

Address Access

Time

(2) TAVQV

VCC = 4.5 and

5.5V, Note 3

9, 10, 11

-55oC

 TA

 +125oC

-120

-220

-320

ns

Chip Enable

Pulse Negative

Width

(5) TELEH

VCC = 4.5 and

5.5V

9, 10, 11

-55oC

 TA

 +125oC

120

-

200

-

300

-

ns

Chip Enable

Pulse Positive

Width

(6) TEHEL

VCC = 4.5 and

5.5V

9, 10, 11

-55oC

 TA

 +125oC

50

-

90

-

120

-

ns

Address Setup

Time

(7) TAVEL

VCC = 4.5 and

5.5V

9, 10, 11

-55oC

 TA

 +125oC

0-

20

-

20

-

ns

Address Hold

Time

(8) TELAX

VCC = 4.5 and

5.5V

9, 10, 11

-55oC

 TA

 +125oC

40

-

50

-

50

-

ns

Write Enable

Pulse Width

(9) TWLWH

VCC = 4.5 and

5.5V

9, 10, 11

-55oC

 TA

 +125oC

120

-

200

-

300

-

ns

Write Enable

Pulse Setup

Time

(10) TWLEH

VCC = 4.5 and

5.5V

9, 10, 11

-55oC

 TA

 +125oC

120

-

200

-

300

-

ns

Write Enable

Pulse Hold Time

(11) TELWH

VCC = 4.5 and

5.5V

9, 10, 11

-55oC

 TA

 +125oC

120

-

200

-

300

-

ns

Data Setup Time

(12) TDVWH

VCC = 4.5 and

5.5V

9, 10, 11

-55oC

 TA

 +125oC

50

-120

-200

-

ns

Data Hold Time

(13) TWHDX

VCC = 4.5 and

5.5V

9, 10, 11

-55oC

 TA

 +125oC

0-0-0-

ns

Write Data Delay

Time

(14) TWLDV

VCC = 4.5 and

5.5V

9, 10, 11

-55oC

 TA

 +125oC

70

-

80

-

100

-

ns

Early Output

High-Z Time

(15) TWLEL

VCC = 4.5 and

5.5V

9, 10, 11

-55oC

 TA

 +125oC

0-0-0-

ns

Late Output

High-Z Time

(16) TEHWH

VCC = 4.5 and

5.5V

9, 10, 11

-55oC

 TA

 +125oC

0-0-0-

ns

Read or Write

Cycle Time

(17) TELEL

VCC = 4.5 and

5.5V

9, 10, 11

-55oC

 TA

 +125oC

170

-

290

-

420

-

ns

NOTES:

1. All voltages referenced to device GND.

2. Input pulse levels: 0.8V to VCC-2.0V; Input rise and fall times: 5ns (max); Input and output timing reference level: 1.5V; Output load: 1 TTL gate

equivalent, CL = 50pF (min) - for CL greater than 50pF, access time is derated by 0.15ns per pF.

3. TAVQV = TELQV + TAVEL.