VFC110

SBVS021A − OCTOBER 1988 − REVISED APRIL 2007

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7

Table 1. Component Selection Table

FULL-SCALE

FREQUENCY,

EXTERNAL COMPONENTS

FREQUENCY,

fFS

RIN

COS

CINT

4MHz

∗

∗

∗

2MHz

34k

Ω

56pF

∗

1MHz

40k

Ω

150pF

∗

500kHz

58k

Ω

330pF

2nF

100kHz

44k

Ω

2.2nF

10nF

50kHz

88k

Ω

2.2nF

0.1

µF

10kHz

44k

Ω

22nF

0.1

µF

* Use internal component only.

The values given were determined empirically to give the optimal

performance, taking into consideration tradeoffs between linearity

and jitter for each given full-scale frequency of operation. The

capacitors listed were chosen from standard values of NPO ceramic

type capacitors while the resistor values were rounded off. Larger

CINT values may improve linearity, but may also increase frequency

noise.

PULL-UP RESISTOR

The VFC110 frequency output is an open-collector

transistor. A pull-up resistor should be connected from fOUT

to the logic supply voltage, +VL. The output transistor is On

during the one-shot period, causing the output to be a logic

Low. The current flowing in this resistor should be limited

to 8mA to assure a 0.4V maximum logic Low. The value

chosen for the pull-up resistor may depend on the

full-scale frequency and capacitance on the output line.

Excessive capacitance on fOUT will cause a slow, rounded

rising edge at the end of an output pulse. This effect can

be minimized by using a pull-up resistor which sets the

output current to its maximum of 8mA. The logic power

supply can be any positive voltage up to +VS.

ENABLE PIN

If left unconnected, the Enable input will assume a logic

High level, enabling operation. Alternatively, the Enable

input may be connected directly to +VS. Since an internal

pull-up current is included, the Enable input may be driven

by an open-collector logic signal.

A logic Low at the Enable input causes output pulses to

cease. This is accomplished by interrupting the signal path

through the one-shot circuitry. While disabled, all circuitry

remains active and quiescent current is unchanged. Since

no reset current pulses can occur while disabled, any

positive input voltage will cause the integrator op amp to

ramp negatively and saturate at its most negative output

swing of approximately −0.7V.

When the Enable input receives a logic High (greater than

+2V), a reset current cycle is initiated (causing fOUT to go

Low). The integrator ramps positively and normal

operation is established. The time required for the output

frequency to stabilize is equal to approximately one cycle

of the final output frequency plus 1

µs.

2

V

IN

112

11

One−Shot

V

REF

−V

S

413

NC

3

6

8

f

OUT

0kHz to 100kHz

10

+VS

7

5

R

PU

+VL

C

OS

2.2nF

High = Enable

Low = Disable

C

INT

10nF

0V to

+10V

5k

Ω

Gain Trim

44k

Ω

R

IN

NC

14

Figure 2. 100kHz Full-Scale Operation