ADPA7001CHIPS datasheet(13/18 Pages) AD

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Data Sheet

ADPA7001CHIPS

Rev. B | Page 13 of 18

THEORY OF OPERATION

The architecture of the ADPA7001CHIPS medium power

amplifier is shown in Figure 39. The ADPA7001CHIPS uses

four cascaded, four-stage amplifiers operating in quadrature

between six 90° hybrids.

The input signal is divided evenly into two. Then, each signal is

again divided into two, and each of these paths is amplified

through four independent gain stages. Then, the amplified

signals are combined at the output. This balanced amplifier

approach forms an amplifier with a combined gain of 14 dB and

a PSAT value of 21 dBm.

A portion of the RF output signal is directionally coupled to a

diode for detection of the RF output power. When the diode is

dc biased, it rectifies the RF power and makes it available for

measurement as a dc voltage at VDET. To allow temperature

compensation of VDET, an identical and symmetrically located

circuit, minus the coupled RF power, is available via VREF.

Taking the difference of VREF – VDET provides a temperature

compensated signal that is proportional to the RF output. (see

Figure 36).

The 90° hybrids ensure that the input and output return losses

are greater than or equal to 15 dB and 12 dB, respectively. See

the application circuits shown in Figure 43 and Figure 44 for

further details on biasing the various blocks.

RFIN

RFOUT

VDET

VREF

90° COUPLER

DIRECTIONAL

COUPLER

FOUR STAGE BALANCED AMPLIFIER

90° COUPLER

FOUR STAGE BALANCED AMPLIFIER

90° COUPLER

Figure 39. ADPA7001CHIPS Architecture

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