8

FIGURE 1. DPLL USING BOTH PHASE DETECTORS IN A RIPPLE-CANCELLATION SCHEME

FIGURE 2. DPLL USING EXCLUSIVE-OR PHASE DETECTION

FIGURE 3. TIMING DIAGRAM: I/DOUT IN-LOCK CONDITION

DIVIDE-BY-K

COUNTER

ENCTR

KCP

D/U

CARRY

BORROW

XORPDOUT

JJ

ECPD

K

FF

ECPDOUT

φA

1

φB

φA

2

DIVIDE-BY-N

COUNTER

I/DOUT

I/DCP

I/D CIRCUIT

2NfC

MfC

fOUT

φ

OUT

fIN

φ

IN

DIVIDE-BY-K

COUNTER

KCP

D/U

CARRY

BORROW

XORPDOUT

φA

1

φB

DIVIDE-BY-N

COUNTER

I/DOUT

I/DCP

I/D CIRCUIT

2NfC

MfC

fOUT

φ

IN

fOUT

φ

OUT

CARRY PULSE

(INTERNAL SIGNAL)

BORROW PULSE

(INTERNAL SIGNAL)

I/DCP INPUT

I/DOUT OUTPUT

CD54HC297, CD74HC297, CD74HCT297

CD54HC297, CD74HC297, CD74HCT297