CDC319

1-LINE TO 10-LINE CLOCK DRIVER

WITH I2C CONTROL INTERFACE

SCAS590A – DECEMBER 1997 – REVISED OCTOBER 2001

10

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

CAPACITIVE LOAD

vs

SUPPORTED MAXIMUM CLOCK FREQUENCY

30

10

f – Supported Maximum Clock Frequency – MHz

130

50

50

70

90

110

15

20

25

30

35

40

45

120

100

80

60

40

60

55

140

150

TA = 55°C

TJ = 130°C

VDD = 3.465 V

TA = 70°C

TJ = 130°C

VDD = 3.6 V

NOTES: A. With a total capacitive load of 20 pF for each output, the CDC319 is capable of running up to about 125 MHz. A lower capacitive

load will allow higher application frequencies, up to 133 MHz (140 MHz).

B. CPD for the CDC319 is about 25 pF per output (21 pF if CL < 20 pF)

P(total) = VDD2

× CPD × FO × N + (VOH – VOL)2 × CL × FO × N + DC load

where:

N = number of switching outputs

FO = clock frequency

Package thermal impedance (junction-to-ambient) = 92.4

°C/W

Maximum junction temperature = 150

°C (<125°C recommended)

Figure 4