| Electronic Components Datasheet Search |
|
P240 Datasheet(PDF) 30 Page - Altera Corporation |
|
|
|||||||||||||||||||||||||||||
P240 Datasheet(HTML) 30 Page - Altera Corporation |
|
30 / 348 page ![]() 2–4 Chapter 2: Logic Elements and Logic Array Blocks in the Cyclone III Device Family Logic Array Blocks Cyclone III Device Handbook December 2011 Altera Corporation Volume 1 Arithmetic Mode Arithmetic mode is ideal for implementing adders, counters, accumulators, and comparators. An LE in arithmetic mode implements a 2-bit full adder and basic carry chain (Figure 2–3). LEs in arithmetic mode can drive out registered and unregistered versions of the LUT output. Register feedback and register packing are supported when LEs are used in arithmetic mode. Figure 2–3 shows LEs in arithmetic mode. The Quartus II Compiler automatically creates carry chain logic during design processing. You can also manually create the carry chain logic during design entry. Parameterized functions, such as LPM functions, automatically take advantage of carry chains for the appropriate functions. The Quartus II Compiler creates carry chains longer than 16 LEs by automatically linking LABs in the same column. For enhanced fitting, a long carry chain runs vertically, which allows fast horizontal connections to M9K memory blocks or embedded multipliers through direct link interconnects. For example, if a design has a long carry chain in a LAB column next to a column of M9K memory blocks, any LE output can feed an adjacent M9K memory block through the direct link interconnect. If the carry chains run horizontally, any LAB which is not next to the column of M9K memory blocks uses other row or column interconnects to drive a M9K memory block. A carry chain continues as far as a full column. Logic Array Blocks Logic array blocks (LABs) contain groups of LEs. Topology Each LAB consists of the following features: ■ 16 LEs Figure 2–3. Cyclone III Device Family LEs in Arithmetic Mode clock (LAB Wide) ena (LAB Wide) aclr (LAB Wide) CLRN D Q ENA sclear (LAB Wide) sload (LAB Wide) Register Chain Output Row, Column, and Direct link routing Row, Column, and Direct link routing Local Routing Register Feedback Three-Input LUT Three-Input LUT cin (from cout of previous LE) data2 data1 cout Register Bypass data4 data3 Register Chain Connection Packed Register Input |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |