The AFE5812 also includes a digital in-phase and quadrature (I/Q) demodulator and a low-pass decimation

filter. The main purpose of the demodulation block is to reduce the LVDS data rate and improve overall system

power efficiency. The I/Q demodulator can accept ADC output with up to 65 MSPS sampling rate and 14-bit

resolution. For example, after digital demodulation and 4× decimation filtering, the data rate for either in-phase

or quadrature output is reduced to 16.25 MSPS and the data resolution is improved to 16 bits, consequently.

Hence, the overall LVDS trace reduction can be a factor of 2. This demodulator can be bypassed and powered

down completely if it is not needed.

The AFE5812 is available in a 15mm × 9mm, 135-pin BGA package, and it is specified for operation from –40°C

to 85°C.

Package Information

PART NUMBER

PACKAGE(1)

PACKAGE SIZE(2)

AFE5812

ZCF (NFBGA, 135)

9mm × 15mm

(1)

For all available packages, see Section 7.

(2)

The package size (length × width) is a nominal value and includes pins, where applicable.

SPI

LNA

VCAT

0 to -40 dB

SPI Logic

16X CLKP

IN

PGA

24, 30dB

3

rd LP Filter

10, 15, 20, 30

35, 50 MHz

16 Phases

Generator

CW Mixer

Summing

Amplifier/ Filter

16X CLKN

1X CLK

CW I/Q Vout

AFE5812 with Demodulator : 1 of 8 Channels

14 Bit

ADC

LVDS

OUT

Reference

Reference

Differential

TGC Vcntl

EXT/INT

REFM/P

Digital

Demod &

Dec Filter

LVDS

Serializer

Logic

Control

DeMod

Control

Simplified Diagram

AFE5812

SLOSEC2 – MARCH 2024

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