bq2016

GAS GAUGE IC FOR

HIGH DISCHARGE RATES

SLUS475A– JANUARY 2001 – REVISED NOVEMBER 2002

14

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

error summary (continued)

The display becomes active during charge if the NAC registers are counting at a rate equivalent to VSR > 2 mV

or discharge if the NAC registers are counting at a rate equivalent to VSR < –2 mV. When DISP is pulled low,

the segment output becomes active for 4 seconds. LED1 blinks at a 4-Hz rate whenever NAC is less than 6%

of LMD or VSB ≤ VEDV.

Table 8. Display Mode

LED1

LED2

LED3

LED4

LED5

NAC / LMD

ON

ON

ON

ON

ON

80 – 100%

ON

ON

ON

ON

OFF

60 –

< 80%

ON

ON

ON

OFF

OFF

40 –

< 60%

ON

ON

OFF

OFF

OFF

20 –

< 40%

ON

OFF

OFF

OFF

OFF

6

< 20%

BLINK

OFF

OFF

OFF

OFF

< 6%

BLINK

OFF

OFF

OFF

OFF

VSB ≤ VEDV

RBI input

The RBI input pin should be used with a storage capacitor or external supply to provide backup potential to the

internal bq2016 registers when VCC drops below 3.0 V. VCC is output on RBI when VCC is above 3.0 V. If an

external supply (such as the bottom series cell) is the backup source, then an external diode is required for

isolation.

initialization

The bq2016 can be initialized by removing VCC and grounding the RBI pin for 5 seconds or by a command over

the serial port. The HDQ port reset command requires writing 78h to register CMDWD.

microregulator

A REG output is provided to regulate an external low-threshold JFET to supply power to the bq2016 based circuit

from the series cells. The REG output maintains VCC to the bq2016 at 3.3 V.

communicating with the bq2016

The bq2016 includes a simple single-pin (HDQ referenced to Vss) serial data interface. A host processor uses

the interface to access various bq2016 registers. By adding a single contact to the battery pack, the host can

easily monitor the battery characteristics. The open-drain HDQ pin on the bq2016 should be pulled up by the

host system or pulled down to ground.

The interface uses a command-based protocol, in which the host processor sends a command byte to the

bq2016. The command directs the bq2016 to either store the next eight bits of data received to a register

specified by the command byte or output the eight bits of data specified by the command byte. The

communication protocol is asynchronous return-to-one. Command and data bytes consist of a stream of eight

bits that have a maximum transmission rate of 5K bits/s. The least-significant bit of a command or data byte

is transmitted first. The protocol is simple enough that it can be implemented by most host processors using

either polled or interrupt processing. Data input from the bq2016 may be sampled using the pulse-width capture

timers available on some microcontrollers.

If a communication error occurs (e.g., tCYCB > 250µs), the bq2016 should be sent a BREAK to reinitiate the serial

interface. A BREAK is detected when the HDQ pin is driven to a logic-low state for a time tB or greater. The HDQ

pin should then be returned to its normal ready-high logic state for a time tBR. The bq2016 is now ready to

receive a command from the host processor.