Block Digram

SPI ROM

BOM

Optional

BOM

Optional

BOM

Optional

Intel® Alder

Lake-N &

Amston Lane

Processor

(9 to 12W)

ADLN

2 x SODIMM

1 x DDI

1 x TCP

1 x eDP

1 x HDA

1x SATA III

4 x PCIE III (Optional)

2 x USB 3.2 GEN1

6 x USB 2.0

1 x SPI

1 x eSPI

DDIA_eDP (0 - 1)

Display Spec.

HDMI 2.0: 4096 x 2160@60Hz

DP 1.4a UHBR10: 4096 x 2304@60Hz

eDP 1.4b HBR3: 4096 x 2304@60Hz

LPDDR5 x 32-4800MT/s

Channel A

CAN BUS Port 1 to 2

PCIE3.0 x3 (PCIE9-11)

Intel® CPU

SMARC Connector

SMARC ver. 2.2

Max: PCIe x4 Device

BOM

Optional

I2C

UART x 2 (UART 2 TX/RX/CTS/RTS & UART3 Tx/Rx)

eDP to

LVDS

LVDS Channel B (default)

LVDS Channel A

SPI

DDIA_eDP (2 - 3) eDP 1.4

CH7513/

7511B

EC

IT5571

eMMc

Transcend 64GB/128GB

LPDDR5 4800MHz CH-A

Memory Down

LPDDR5 4800MHz CH-B

Memory Down

LPDDR5 x 32 4800MT/s

Channel B

DDIA_eDP

LVDS

DDIB (0 - 3) DP 1.2/HDMI 2.0

TCP0 (0 - 3) DP 1.2/HDMI 2.0

eDP/LVDS

DDIB

TCP0

PCIE3.0 x1 (PCIE2)

LAN

I226-V

LAN

I226-V

PCIE3.0 x1 (PCIE7)

LAN1 MDI x 4

BOM Optional For CS0 From MB or CB

SPI

GSPI

ACPI/BOOT SEL/PCIE_RST_LID/USB VBUS DET

I2C_PM

I2C_MDIO

UART 1 & 4

GBE0

GBE1

HDA

GPIO 0 to 13

FAN

PWM/IN

14 GPIO

SATA/PCIE BOM Optional Default : SATA

SMBUS

SML 1

eSPI 1

eSPI1

UART 2 & 3

UART 1 & 4

LAN2 MDI x 4

I2C0

I2C1

I2C_CAM0

I2C_CAM1

I2S0

I2S1

HDA

I2C_GP

I2C2

PCIE A to C

SATA

USB3.21 to 2

PCIE D

LVDS_I2C

BOM Optional

SATA/PCIE3.0 x1 (PCIE12)

USB 3.2 x 2 (PCIE2-3)

USB 2.0 x 6 (USB 2_P1 to USB 2_P5)

USB2.00 to 5

CAN BUS 1 to 2

10-pin (5A Per pin)

eSPI 0

USB 2.0 x 1 (USB 2_P6)

eSPI 0

GSPI

F81604

USB 2.0 To CAN

* All specifications and photos are subject to change without notice.

© 2025 Axiomtek Co., Ltd. All rights reserved.

Updated Feb. 26, 2025.