ADS7809

5

SBAS017C

www.ti.com

PIN #

NAME

DESCRIPTION

PIN ASSIGNMENTS

1R1IN

Analog Input. See Table I and Figure 4 for input range connections.

2

AGND1

Analog Ground. Used internally as ground reference point. Minimal current flow.

3R2IN

Analog Input. See Table I and Figure 4 for input range connections.

4R3IN

Analog Input. See Table I and Figure 4 for input range connections.

5

CAP

Reference Buffer Capacitor. 2.2

µF Tantalum to ground.

6

REF

Reference Input/Output. Outputs internal 2.5V reference. Can also be driven by external system reference. In both cases,

bypass to ground with a 2.2

µF Tantalum capacitor.

7

AGND2

Analog Ground

8

SB/BTC

Select Straight Binary or Binary Two’s Complement data output format. If HIGH, data will be output in a Straight Binary format. If

LOW, data will be output in a Binary Two’s Complement format.

9

EXT/INT

Select External or Internal Clock for transmitting data. If HIGH, data will be output synchronized to the clock input on DATACLK. If

LOW, a convert command will initiate the transmission of the data from the previous conversion, along with 16 clock pulses output

on DATACLK.

10

DGND

Digital Ground

11

SYNC

Synch Output. If EXT/INT is HIGH, either a rising edge on R/C with CS LOW or a falling edge on CS with R/C HIGH will output a

pulse on SYNC synchronized to the external DATACLK.

12

DATACLK

Either an input or an output depending on the EXT/INT level. Output data will be synchronized to this clock. If EXT/INT is LOW,

DATACLK will transmit 16 pulses after each conversion, and then remain LOW between conversions.

13

DATA

Serial Data Output. Data will be synchronized to DATACLK, with the format determined by the level of SB/BTC. In the external clock

mode, after 16 bits of data, the ADS7809 will output the level input on TAG as long as CS is LOW and R/C is HIGH (see Figure 3). If

EXT/INT is LOW, data will be valid on both the rising and falling edges of DATACLK, and between conversions DATA will stay at the

level of the TAG input when the conversion was started.

14

TAG

Tag Input for use in external clock mode. If EXT/INT is HIGH, digital data input on TAG will be output on DATA with a delay of 16

DATACLK pulses as long as CS is LOW and R/C is HIGH. See Figure 3.

15

R/C

Read/Convert Input. With CS LOW, a falling edge on R/C puts the internal sample-and-hold into the hold state and starts a conversion.

When EXT/INT is LOW, this also initiates the transmission of the data results from the previous conversion. If EXT/INT is HIGH, a

rising edge on R/C with CS LOW, or a falling edge on CS with R/C HIGH, transmits a pulse on SYNC and initiates the transmission of

data from the previous conversion.

16

CS

Chip Select. Internally OR’ed with R/C.

17

BUSY

Busy Output. Falls when a conversion is started, and remains LOW until the conversion is completed and the data is latched into the

output shift register. CS or R/C must be HIGH when BUSY rises, or another conversion will start without time for signal acquisition.

18

PWRD

Power Down Input. If HIGH, conversions are inhibited and power consumption is significantly reduced. Results from the previous

conversion are maintained in the output shift register.

19

VANA

Analog Supply Input. Nominally +5V. Connect directly to pin 20, and decouple to ground with 0.1

µF ceramic and 10µF tantalum

capacitors.

20

VDIG

Digital Supply Input. Nominally +5V. Connect directly to pin 19. Must be

≤ V

ANA.

PIN CONFIGURATION

V

DIG

V

ANA

PWRD

BUSY

CS

R/C

TAG

DATA

DATACLK

SYNC

R1

IN

AGND1

R2

IN

R3

IN

CAP

REF

AGND2

SB/BTC

EXT/INT

DGND

1

2

3

4

5

6

7

8

9

10

20

19

18

17

16

15

14

13

12

11

ADS7809

ANALOG

CONNECT R1IN

CONNECT R2IN

INPUT

VIA 200

Ω

VIA 100

Ω

CONNECT R3IN

RANGE

TO

TO

TO

IMPEDANCE

±10V

VIN

AGND

CAP

22.9k

Ω

±5V

AGND

VIN

CAP

13.3k

Ω

±3.33V

VIN

VIN

CAP

10.7k

Ω

0V to 10V

AGND

VIN

AGND

13.3k

Ω

0V to 5V

AGND

AGND

VIN

10.0k

Ω

0V to 4V

VIN

AGND

VIN

10.7k

Ω

TABLE I. Input Range Connections. See Figure 4 for complete

information.

FIGURE 1. Basic Conversion Timing.

MODE Acquire

t

4

t

5

t

1

t

3

t

7

t

6

Convert

Acquire

t

2

BUSY

CS, R/C