www.renesas.com

© 2024 Renesas Electronics Corporation. All rights reserved.

2024.11

H8S CPU subsystem (H8S C200)

16-bit CPU IP

Overview

H8S is a high speed 16-bit CPU with an internal 32-bit architecture.

It is upward-compatible with H8/300 and H8/300H CPUs on an object level.

This subsystem IP, which is for IP license, supports basic and simple microcontroller functions,

including bus controller (BSC), interrupt controller (INT), timers, serial communication interface (SCI)

and on-chip debug functions.

Optional information packages for H8/327, H8/337, H8/3048, H8S/2655 and H8S/2355 approximation

are also available.

Key Features

▪

An original subsystem for SoCs other than

microcomputers

▪

3 type interfaces available to connect user

functions or IPs

− compiled memory interface

− external memory interface

− peripheral bus interface

CTPD-24-163

R06PF0005EJ0102

▪

4 type timers

− 16-bit free-running timer (FRT)

− 8-bit timer

− 14-bit PWM timer

− Watchdog timer (WDT)

▪

Serial communication interface(SCI)

▪

Supporting on-chip debug functions (option)

▪

Applicable to various processes and FPGAs

▪

Handy size

Block Diagram

H8S C200 IP

CPU

INT

Timers

SCI

External

memory

interface

Compiled memory

interface

Peripheral bus

interface

BSC