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DRV201AYMBRB Datasheet(PDF) 7 Page - Texas Instruments |
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DRV201AYMBRB Datasheet(HTML) 7 Page - Texas Instruments |
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7 / 28 page  DRV201A www.ti.com SLVSBN6A – JUNE 2013 – REVISED AUGUST 2015 6.6 Data Transmission Timing Requirements VBAT = 3.6 V ±5%, TA = 25ºC, CL = 100 pF (unless otherwise noted) MIN NOM MAX UNIT f(SCL) Serial clock frequency 100 400 kHz SCL = 100 KHz 4.7 tBUF Bus Free Time Between Stop and Start Condition µs SCL = 400 KHz 1.3 SCL = 100 KHz 50 tSP Tolerable spike width on bus ns SCL = 400 KHz SCL = 100 KHz 4.7 tLOW SCL low time µs SCL = 400 KHz 1.3 SCL = 100 KHz 4 µs tHIGH SCL high time SCL = 400 KHz 600 ns SCL = 100 KHz 250 tS(DAT) SDA → SCL setup time ns SCL = 400 KHz 100 SCL = 100 KHz 4.7 µs tS(STA) Start condition setup time SCL = 400 KHz 600 ns SCL = 100 KHz 4 µs tS(STO) Stop condition setup time SCL = 400 KHz 600 ns SCL = 100 KHz 0 3.45 tH(DAT) SDA → SCL hold time µs SCL = 400 KHz 0 0.9 SCL = 100 KHz 4 µs tH(STA) Start condition hold time SCL = 400 KHz 600 ns SCL = 100 KHz 1000 tr(SCL) Rise time of SCL Signal ns SCL = 400 KHz 300 SCL = 100 KHz 300 tf(SCL) Fall time of SCL Signal ns SCL = 400 KHz 300 SCL = 100 KHz 1000 tr(SDA) Rise time of SDA Signal ns SCL = 400 KHz 300 SCL = 100 KHz 300 tf(SDA) Rise time of SDA Signal ns SCL = 400 KHz 300 Copyright © 2013–2015, Texas Instruments Incorporated Submit Documentation Feedback 7 Product Folder Links: DRV201A |
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