LM48821, LM48821TLEVAL

www.ti.com

SNAS354A – JUNE 2007 – REVISED MAY 2013

APPLICATION INFORMATION

Figure 56. I2C Timing Diagram

Figure 57. I2C Bus Format

Table 1. Chip Address

D7

D6

D5

D4

D3

D2

D1

D0

Chip Address

1

1

1

0

1

1

0

0

Table 2. Control Registers

D7

D6

D5

D4

D3

D2

D1

D0

LF

RT

Volume Control

VD4

VD3

VD2

VD1

VD0

MUTE

ENABLE

ENABLE

I2C VOLUME CONTROL

The LM48821 can be configured in 32 different gain steps by forcing I2C volume control bits to a desired gain

according to Table 3.

Copyright © 2007–2013, Texas Instruments Incorporated

Submit Documentation Feedback

15

Product Folder Links: LM48821 LM48821TLEVAL