0

1

2

3

4

5

0

20

40

60

80

100

120

140

160

0

2

4

6

8

10

12

14

16

ISD(A)

VSD(REG)

Q1 = IRF7495PDF

VGATE

VSD

LM5051

SNVS702D – OCTOBER 2011 – REVISED MARCH 2013

www.ti.com

The LM5051 is designed to regulate the MOSFET gate to source voltage if the voltage across the MOSFET

source and drain pins falls below the VSD(REG) voltage of 20 mV (typical). If the MOSFET current decreases to the

point that the voltage across the MOSFET falls below the VSD(REG) voltage regulation point of 12 mV (typical), the

GATE pin voltage will be decreased until the voltage across the MOSFET is regulated at 12 mV (typical). If the

drain to source voltage is greater thanVSD(REG) voltage the gate voltage will increase.

Figure 28. VSD and VGATE vs ILOAD with IRF7495PDF

When the power supply voltages are within a few milli-volts of each other, this regulation method ensures that

the load current transitions between them without any abrupt on and off oscillations. The current flowing through

the MOSFET in each OR-ing circuit depends on the RDS(ON) of the MOSFETs, how close the power supply

voltages are set, and the load regulation of the supplies.

If the MOSFET current reverses, possibly due to failure of the input supply, such that the voltage across the

LM5051 INN pin is 5 mV (typical) more positive than INP/VSS pin (VSD(REV) + ΔVSD(REV)) the LM5051 will quickly

discharge the MOSFET gate through a strong GATE pin to INP/VSS pin discharge path. A reverse current

though the MOSFET is required to turn the gate drive off. If a single operating supply is removed from the OR-

ing array, the gate drive will not be discharged since there is no reverse current through the MOSFET to trip the

reverse comparator.

If the input supply fails abruptly, as would occur if the supply was shorted directly to ground, a reverse current

will temporarily flow through the MOSFET until the gate can be fully discharged. This reverse current is sourced

from the load capacitance and from the parallel connected supplies. The LM5051 responds to a voltage reversal

condition typically within 34 ns. The actual time required to turn off the MOSFET will depend on the charge held

by gate capacitance of the MOSFET being used. A MOSFET with 47 nF of effective gate capacitance can be

turned off in typically 90 ns. This fast turn-off time minimizes voltage disturbances at the output, as well as the

current transients from the redundant supplies.

OFF PIN

The OFF pin is used to disable the active OR-ing control circuitry, and to discharge the MOSFET Gate. The OFF

pin has an internal pull-down (4.6

μA typical) which will, by default, keep the active OR-ing control circuitry

enabled. If the OFF pin function is not needed, this pin can be left open or connected to the INP/VSS pin. Pulling

the OFF pin above the VOFF(IH) threshold of 1.50V (typical) will disable the active OR-ing control circuitry and

discharge the MOSFET Gate. The VOFF threshold has a typical hysteresis of 20mV. It is recommended that the

OFF pin be pulled cleanly, and promptly, through the VOFF(IH) threshold region to prevent any aberrant behavior.

The OFF pin must not be pulled higher than 5.5V above the INP/VSS pin.

nFGD PIN

The nFGD pin is an open Drain output pin and is controlled by status of the Forward comparator. When the

voltage on INN pin is more negative than the VSD(TST) threshold voltage (285 mV typical) the nFGD pin will

conduct current to the INP/VSS pin. During normal Active OR-ing, when the MOSFET is ON, the INN pin voltage

should be less than approximately -100mV and the nFGD pin will be logic high. When the MOSFET is OFF and

current is flowing through the body diode of the MOSFET, the INN pin voltage will be approximately -600 mV and

the nFGD pin will be logic low.

12

Submit Documentation Feedback

Copyright © 2011–2013, Texas Instruments Incorporated

Product Folder Links: LM5051