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LM5051MA/NOPB Datasheet(PDF) 2 Page - Texas Instruments |
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LM5051MA/NOPB Datasheet(HTML) 2 Page - Texas Instruments |
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2 / 27 page ![]() LINE VCC nFGD OFF GATE INP/VSS INP/VSS INN 1 2 3 4 5 6 7 8 PS1 PS2 INN GATE INP/VSS INN GATE INP/VSS RLOAD LM5051 LINE LINE VCC D D S S VCC LM5051 LM5051 SNVS702D – OCTOBER 2011 – REVISED MARCH 2013 www.ti.com Figure 2. Typical Redundant Supply Configuration Connection Diagram Top View Device Pin 5 (INP) is internally connected to Device Pin 7 (VSS) Figure 3. LM5051MA 8-Lead SOIC D Package PIN DESCRIPTIONS Pin # Name Function Power supply pin to bias the internal 12V zener shunt regulator at the 1 LINE VCC pin through an internal 50 k Ω (typical) series resistor. See the APPLICATION INFORMATION section. Connection to the internal 12V zener shunt voltage regulator. Bypass this pin with minimum 0.1 μF capacitor to the VSS pin. This pin can be 2 VCC biased via an external resistor rather than via the internal resistor from the LINE pin (pin 1). See the APPLICATION INFORMATION section. FET Test Mode control input. Logic low or open state at the OFF pin will deactivate the FET Test Mode and allow normal operation. A logic high state at the OFF pin will pull the GATE pin low and turn off the 3 OFF external MOSFET. If the body diode forward voltage of the MOSFET (from source to drain) is greater than 260mV the nFGD pin will indicate that the MOSFET is not shorted by pulling to the active low state. Open drain output for the FET Test circuit. An active low state on nFGD indicates that the forward voltage (from source to drain) of the external 4 nFGD MOSFET is greater than 260 mV typical. The nFGD pin requires an external pull-up resistor to a voltage not higher than VSS + 5.5V. 5 INP/VSS See device Pin 7. 6 INN Voltage sense connection to the external MOSFET Drain pin Internally connected to device Pin 5. Negative supply voltage connection and MOSFET voltage sense connected to the external 7 INP/VSS MOSFET common source connection. All device voltages and currents are referenced to this pin, unless otherwise stated. See the INP/VSS PINS section. 2 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: LM5051 |
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