ADS1202IPWR datasheet(13/26 Pages) TI2

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ADS1202

SBAS275B

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The code generator receives the clock signal from MUX1 and

generates the delta-sigma modulator clock (CLK) divided as

half clock (CLK/2) and quarter clock (CLK/4). At the same

time, the continuous data stream (DATA) coming from the

delta-sigma modulator is elaborated by the Code Generator.

Twinned binary coding (also known as split phase or Manches-

ter coding) is implemented and then output from the code

generator to MUX3.

MUX3 selects the source of the output bit stream data,

MDAT. The control signal coming from the decoder controls

the input source of MDAT. Two signals are coming in to the

MUX3, one directly from the delta-sigma modulator and the

other from the code generator. The control signal from the

decoder can select two different output modes on the signal

MDAT: a bit stream from a delta-sigma modulator, or twinned

binary coding of the same signal.

The last control signal from the decoder controls MUX4.

MUX2 selects the input or output clock, the MCLK signal.

The control signal coming from the decoder controls the

direction of the clock. One signal entering MUX4 from MUX2

comes as a clock signal OCLK. Another signal leaves MUX4

and provides an input to MUX1 as an external clock, EXTCLK.

The control signal from the decoder can select two different

modes on MCLK, one as an output of the internal clock

signal and another as the input for the external clock signal.

As a function of two control signals (M0 and M1), the

decoder circuit, using five control signals, will set multiplex-

ers in order to obtain the desired mode of operation.

DIFFERENT MODES OF OPERATION

Figure 5 presents mode selectors (input signals M0 and M1)

that enter the flexible interface circuit and decoder that

decodes the input code, and select the desired mode of

operation. With two control lines it is possible to select four

different modes of operation mode 0, mode 1, mode 2, and

mode 3, which are shown in Table I.

MODE

DEFINITION

Internal Clock, Synchronous Data Output

LOW

Internal Clock, Synchronous Data Output,

LOW

HIGH

Half Output Clock Frequency

Internal Clock, Manchester Coded Data Output

HIGH

LOW

External Clock, Synchronous Data Output

HIGH

TABLE I. Mode Definition and Description.

FIGURE 5. Flexible Interface Block Diagram.

Decoder

Interface Circuit

∆∑

Modulator

CLK/2

OCLK

EXTCLK

INTCLK

CLK/4

MUX3

MUX1

MUX2

MDAT

MUX4

AIN

MCLK

CLK

DATA

Code

Generator

Oscillator

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