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SPECIFICATIONS, ADS7868

ADS7866

ADS7867

ADS7868

SLAS465 – JUNE 2005

At –40

°C to 85°C, f

SAMPLE = 280 KSPS and fSCLK = 3.4 MHz if 1.6 V ≤ VDD ≤ 3.6 V; fSAMPLE = 140 KSPS and fSCLK = 1.7 MHz if

1.2 V

≤ V

DD < 1.6 V (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

SYSTEM PERFORMANCE

Resolution

8

Bits

No missing codes

8

Bits

Integral linearity

–0.5

0.5

LSB(1)

Differential linearity

–0.5

0.5

LSB

1.2 V

≤ V

DD < 1.6 V

–0.5

0.5

Offset error(2)

LSB

1.6 V

≤ V

DD ≤ 3.6 V

–0.5

0.5

1.2 V

≤ V

DD < 1.6 V

–0.5

0.5

Gain error(3)

LSB

1.6 V

≤ V

DD ≤ 3.6 V

–0.5

0.5

1.2 V

≤ V

DD < 1.6 V

–1

1

Total unadjusted error(4)

LSB

1.6 V

≤ V

DD ≤ 3.6 V

–1

1

SAMPLING DYNAMICS (See Timing Characteristics Section)

tCONVERT

Conversion time

fSCLK = 3.4 MHz, 9 SCLK cycles

2.647

µs

tSAMPLE

Acquisition time

fSCLK = 3.4 MHz, 1.6 V ≤ VDD ≤ 3.6 V

0.64

µs

fSAMPLE

Throughput rate

fSCLK = 3.4 MHz, 1.6 V ≤ VDD ≤ 3.6 V

280

KSPS

Aperture delay

10

ns

Aperture jitter

40

ps

DYNAMIC CHARACTERISTICS

fSAMPLE = 100 KSPS, fIN = 30 kHz, 1.2 V ≤ VDD < 1.6 V

49

Signal-to-noise

SINAD

dB

and distortion

fSAMPLE = 200 KSPS, fIN = 30 kHz, 1.6 V ≤ VDD ≤ 3.6 V

49

49.4

fSAMPLE = 100 KSPS, fIN = 30 kHz, 1.2 V ≤ VDD < 1.6 V

49.4

SNR

Signal-to-noise ratio

dB

fSAMPLE = 200 KSPS, fIN = 30 kHz, 1.6 V ≤ VDD ≤ 3.6 V

49.8

fSAMPLE = 100 KSPS, fIN = 30 kHz, 1.2 V ≤ VDD < 1.6 V

–65

Total harmonic

THD

dB

distortion(5)

fSAMPLE = 200 KSPS, fIN = 30 kHz, 1.6 V ≤ VDD ≤ 3.6 V

–72

-66

fSAMPLE = 100 KSPS, fIN = 30 kHz, 1.2 V ≤ VDD < 1.6 V

67

Spurious free dynamic

SFDR

dB

range

fSAMPLE = 200 KSPS, fIN = 30 kHz, 1.6 V ≤ VDD ≤ 3.6 V

66

67

At 0.1 dB, 1.2 V

≤ V

DD < 1.6 V

2

At 0.1 dB, 1.6 V

≤ V

DD ≤ 3.6 V

4

Full-power bandwidth(6)

MHz

At 3 dB, 1.2 V

≤ V

DD < 1.6 V

3

At 3 dB, 1.6 V

≤ V

DD ≤ 3.6 V

8

ANALOG INPUT

Full-scale input span(7)

VIN – GND

0

VDD

V

CS

Input capacitance

12

pF

Input leakage current

–1

1

µA

DIGITAL INPUT

Logic family, CMOS

1.2 V

≤ V

DD < 1.6 V

0.7

×V

DD

3.6

1.6 V

≤ V

DD < 1.8 V

0.7

×V

DD

3.6

VIH

Input logic high level

V

1.8 V

≤ V

DD < 2.5 V

0.7

×V

DD

3.6

2.5 V

≤ V

DD ≤ 3.6 V

2

3.6

(1)

LSB = Least Significant BIt

(2)

The difference in the first code transition 000...000 to 000...001 from the ideal value of GND + 1 LSB.

(3)

The difference in the last code transition 011...111 to 111...111 from the ideal value of VDD - 1 LSB with the offset error removed.

(4)

The absolute difference from the ideal transfer function of the converter. This specification is similar to INL error except the effects of

offset error and gain error are included.

(5)

The 2nd through 10th harmonics are used to determine THD.

(6)

Input frequency where the amplitude of the digitized signal has decreased by 0.1 dB or 3 dB.

(7)

Ideal input span which does not include gain or offset errors.

7