Ranges

FREQUENCY RESPONSE

Resolution

0

-10

-20

-30

-40

-50

0.1

t

INT

100

t

INT

1

t

INT

10

t

INT

Frequency

Data Format

OPERATION SETTINGS

DDC316

SBAS370A – MARCH 2008 – REVISED APRIL 2009......................................................................................................................................................... www.ti.com

There are three different capacitors available on-chip

The frequency response of the DDC316 is set by the

for both sides of every channel in the DDC316. The

front-end

integrators

and

is

consistent

with

a

range control bits (Range[1:0]) change the capacitor

traditional continuous time integrator, as shown in

value for all integrators. Consequently, all inputs and

Figure 8. By adjusting tINT, the user can change the

both sides of each input always have the same

3dB bandwidth and the location of the notches in the

full-scale (FS) range. Table 1 shows the capacitor

response. The frequency response of the ADC that

value selected for each range selection.

follows the front-end integrator is of no consequence

because the converter samples a held signal from the

Table 1. Range Selection

integrators. That is, the input to the ADC is always a

DC signal. Aliasing can occur because the output of

RANGE[1:0]

CF

INPUT RANGE

the front-end integrators are sampled. Whenever the

RANGE

BITS

(pF, typ)

(pC, typ)

frequency of the input signal exceeds one-half of the

1

00

0.75

–0.0469 to 3

sampling rate, the signal folds back down to lower

2

01

1.5

–0.0938 to 6

frequencies.

3

10

3

–0.1876 to 12

The DDC316 provides three different resolutions for

the convenience of the user. The user can select the

resolution needed for the application and the time

available for data retrieval. The three available

resolutions are 16-bit, 14-bit, and 12-bit. The serial

output data from the DDC316 are provided in an

offset binary code, as shown in Table 2. The RES

bits in the configuration register select how many bits

are used in the output word. When 12-bits are

selected, the last four bits are truncated; when 14-bits

are chosen, the last two bits are truncated. Note that

an offset is included in the output to allow slightly

negative inputs (for example, from board leakages)

from clipping the reading. The offset is approximately

1.8% of the positive full-scale.

Figure 8. DDC316 Frequency Response

The DDC316 outputs 12 to 16 bits of data depending

The DDC316 provides different settings of operation

on the selected resolution. The format is straight

to provide flexibility in terms of range, resolution, etc.

binary with an offset to help prevent leakage currents

The settings are programmable using an on-chip

from the printed circuit board (PCB), or the sensors

register and are described in the following sections.

forcing a clipping on the negative full-scale. Table 2

summarizes the ideal output codes for the different

resolutions.

Table 2. Ideal Output Code(1) vs Input Signal

INPUT

IDEAL OUTPUT CODE

IDEAL OUTPUT CODE

IDEAL OUTPUT CODE

SIGNAL

RESOLUTION = 16 BITS

RESOLUTION = 14 BITS

RESOLUTION = 12 BITS

≥ 100% FS

1111 1111 1111 1111

1111 1111 1111 11

1111 1111 1111

0.07019% FS

0000 0100 1100 0000

0000 0100 1100 00

0000 0100 1100

0.02136% FS

0000 0100 1010 0000

0000 0100 1010 00

0000 0100 1010

0.00305% FS

0000 0100 1001 0100

0000 0100 1001 01

0000 0100 1001

0.001525% FS

0000 0100 1001 0011

0000 0100 1001 00

0000 0100 1001

0% FS

0000 0100 1001 0010

0000 0100 1001 00

0000 0100 1001

–1.7857% FS

0000 0000 0000 0000

0000 0000 0000 00

0000 0000 0000

(1)

Excludes the effects of noise, INL, offset, and gain errors.

12

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