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74ACT08M Datasheet(PDF) 1 Page - STMicroelectronics |
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74ACT08M Datasheet(HTML) 1 Page - STMicroelectronics |
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1 / 8 page  1/8 April 2001 s HIGH SPEED: tPD = 4.5ns (TYP.) at VCC = 5V s LOW POWER DISSIPATION: ICC = 2µA(MAX.) at TA=25°C s COMPATIBLE WITH TTL OUTPUTS VIH = 2V (MIN.), VIL = 0.8V (MAX.) s 50 Ω TRANSMISSION LINE DRIVING CAPABILITY s SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 24mA (MIN) s BALANCED PROPAGATION DELAYS: tPLH ≅ tPHL s OPERATING VOLTAGE RANGE: VCC (OPR) = 4.5V to 5.5V s PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 08 s IMPROVED LATCH-UP IMMUNITY DESCRIPTION The 74ACT08 is an advanced high-speed CMOS QUAD 2-INPUT AND GATE fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS tecnology. The internal circuit is composed of 2 stages including buffer output, which enables high noise immunity and stable output. The device is designed to interface directly High Speed CMOS systems with TTL, NMOS and CMOS output voltage levels. All inputs and outputs are equipped with protec- tion circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage. 74ACT08 QUAD 2-INPUT AND GATE PIN CONNECTION AND IEC LOGIC SYMBOLS ORDER CODES PACKAGE TUBE T & R DIP 74ACT08B SOP 74ACT08M 74ACT08MTR TSSOP 74ACT08TTR TSSOP DIP SOP |
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Similar Description - 74ACT08M |
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