INPUT VOLTAGE - OUTPUT VOLTAGE (V)

0

20

40

60

80

100

120

140

0

5

10

15

20

25

30

35

L=10PH

L=4.7PH

L=22PH

LM3485

SNVS178H – JANUARY 2002 – REVISED DECEMBER 2015

www.ti.com

Feature Description (continued)

Figure 23. Propagation Delay

The operating frequency and output ripple voltage can also be significantly influenced by the speed up capacitor

(Cff). Cff is connected in parallel with the high-side feedback resistor, R1. The location of this capacitor is similar

to where a feed-forward capacitor would be located in a PWM control scheme. However, the effect on hysteretic

operation is much different. The output ripple causes a current to be sourced or sunk through this capacitor. This

current is essentially a square wave. Because the input to the feedback pin, FB, is a high impedance node, the

current flows through R2. The end result is a reduction in output ripple and an increase in operating frequency.

When adding Cff, calculate Equation 4 with

α = 1. The value of Cff depends on the desired operating frequency

and the value of R2. A good starting point is 470-pF ceramic at 100-kHz decreasing linearly with increased

operating frequency. Also, as the output voltage is programmed below 2.5 V, the effect of Cff will decrease

significantly.

7.3.2 Current Limit Operation

The LM3485 has a cycle-by-cycle current limit. Current limit is sensed across the VDS of the PFET or across an

additional sense resistor. When current limit is activated, the LM3485 turns off the external PFET for a period of

9 µs (typical). The current limit is adjusted by an external resistor, RADJ.

The current limit circuit is composed of the ISENSE comparator and the one-shot pulse generator. The positive

input of the ISENSE comparator is the ADJ pin. An internal 5.5-µA current sink creates a voltage across the

external RADJ resistor. This voltage is compared to the voltage across the PFET or sense resistor. The ADJ

voltage can be calculated with Equation 5.

VADJ = VIN − (RADJ × 3.0 µA)

where

•

3.0 µA is the minimum ICL-ADJ value

(5)

The negative input of the ISENSE comparator is the ISENSE pin that should be connected to the drain of the

external PFET. The inductor current is determined by sensing the VDS. It can be calculated with Equation 6.

VISENSE = VIN − (RDSON × IIND_PEAK) = VIN − VDS

(6)

12

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