LMK61PD0A2

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SNAS675A – OCTOBER 2015 – REVISED NOVEMBER 2015

7.14 PLL Clock Output Jitter Characteristics

(1) (2)

VDD = 3.3 V ± 5%, TA = -40°C to 85°C

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

RJ

RMS Phase Jitter(3)

fOUT ≥ 100 MHz, All output frequencies and

100

200

fs RMS

(12 kHz – 20 MHz)

output types

(1 kHz – 5 MHz)

RJ

RMS Phase Jitter(3)

fOUT = 62.5 MHz, All output frequencies and

200

400

fs RMS

(12 kHz – 20 MHz)

output types

(1 kHz – 5 MHz)

(1)

Refer to Parameter Measurement Information for relevant test conditions.

(2)

Phase jitter measured with Agilent E5052 signal source analyzer using a differential-to-single ended converter (balun or buffer).

(3)

Ensured by characterization.

7.15 Additional Reliability and Qualification

PARAMETER

CONDITION / TEST METHOD

Mechanical Shock

MIL-STD-202, Method 213

Mechanical Vibration

MIL-STD-202, Method 204

Moisture Sensitivity Level

J-STD-020, MSL3

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