PCF85063TP datasheet(13/52 Pages) NXP

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PCF85063TP

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Product data sheet

Rev. 4 — 6 May 2015

13 of 52

NXP Semiconductors

PCF85063TP

Tiny Real-Time Clock/calendar

8.2.3 Register Offset

The PCF85063TP incorporates an offset register (address 02h) which can be used to

implement several functions, such as:

• Accuracy tuning

• Aging adjustment

• Temperature compensation

[1]

Default value.

For MODE = 0, each LSB introduces an offset of 4.34 ppm. For MODE = 1, each LSB

introduces an offset of 4.069 ppm. The offset value is coded in two’s complement giving a

range of +63 LSB to

64 LSB.

[1]

Default value.

The correction is made by adding or subtracting clock correction pulses, thereby changing

the period of a single second but not by changing the oscillator frequency.

It is possible to monitor when correction pulses are applied. To enable correction interrupt

generation, bit CIE (register Control_1) has to be set logic 1. At every correction cycle a

pulse is generated on pin INT. The pulse width depends on the correction mode. If

multiple correction pulses are applied, an interrupt pulse is generated for each correction

pulse applied.

Table 12.

Offset - offset register (address 02h) bit description

Bit

Symbol

Value

Description

7MODE

offset mode

0[1]

normal mode: offset is made once every two

hours

course mode: offset is made every 4 minutes

6 to 0

OFFSET[6:0]

see Table 13

offset value

Table 13.

Offset values

OFFSET[6:0]

Offset value in

decimal

Offset value in ppm

Normal mode

MODE = 0

Fast mode

MODE = 1

0111111

+63

+273.420

+256.347

0111110

+62

+269.080

+252.278

0000010

+8.680

+8.138

0000001

+4.340

+4.069

0000000[1]

00[1]

0[1]

1111111

1

4.340

4.069

1111110

2

8.680

8.138

1000001

63

273.420

256.347

1000000

64

277.760

260.416

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