G013

f − Frequency − kHz

−140

−120

−100

−80

−60

−40

−20

0

0

5

10

15

20

Input Level = −0.5 dB

Data Points = 8192

C

1

f

2 RC

=

p

PCM1808

SLES177B – APRIL 2006 – REVISED AUGUST 2015

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8.2.2 Detailed Design Procedure

8.2.2.1 Control Pins

The control pins FMT, MD0, and MD1 should be controlled either by biasing with a 10 k

Ω resister to VDD or

GND, or by driving with GPIO from the DSP or audio processor.

8.2.2.2 Master Clock

In this application of the PCM1808 device, a PLL170X series device is used as the master clock source to drive

both the PCM1808 and the DSP or audio processor synchronously. With the addition of the AND gate, the

operation of the PCM1808 device can be halted by control of the MASK bit. A crystal that operates at the

standard audio multiples can also be used.

8.2.2.3 DSP or Audio Processor

In this application, the DSP or audio processor is acting as the audio master, and the PCM1808 is acting as the

audio slave. This means the DSP or audio processor must be able to output audio clocks that the PCM1808 can

use to process audio signals.

8.2.2.4 Input Filters

For the analog input circuit, an ac coupling capacitor should be placed in series with the input. This will remove

the dc component of the input signal. An RC filter can also be implemented to filter out-of-band noise to reduce

aliasing. The equation below can be used to calculate the cutoff frequency of the optional RC filter for the input.

(1)

8.2.3 Application Curve

Figure 27. Output Spectrum

20

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