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PCM3000E/2K Datasheet(PDF) 28 Page - Texas Instruments

Part # PCM3000E/2K
Description  18-BIT STEREO AUDIO CODEC, SINGLE-ENDED ANALOG INPUT/OUTPUT
PDF  44 Pages
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Manufacturer  TI2 [Texas Instruments]
Direct Link  https://www.ti.com
Logo TI2 - Texas Instruments

PCM3000E/2K Datasheet(HTML) 28 Page - Texas Instruments

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PCM3000
PCM3001
SBAS055A – OCTOBER 2000 – REVISED OCTOBER 2004
Table 3. Functions of the Registers
REGISTER NAME
REGISTER BIT(S)
BIT NAME
DESCRIPTION
Register 0
15–11
res
Reserved, should be set to 0
10–9
A[1:0]
Register address 00
8
LDL
DAC attenuation data load control for
Lch
7–0
AL[7:0]
DAC attenuation data for Lch
Register 1
15–11
res
Reserved, should be set to 0
10–9
A[1:0]
Register address 01
8
LDR
DAC attenuation data load control for
Rch
7–0
AR[7:0]
DAC attenuation data for Rch
Register 2
15–11
res
Reserved, should be set to 0
10–9
A[1:0]
Register address 10
8
PDWN
ADC power-down control
7
BYPS
ADC high-pass filter bypass control
6
res
Reserved, should be set to 0
5
ATC
DAC attenuation data mode control
4
IZD
DAC infinite zero detection circuit control
3
OUT
DAC output enable control
2–1
DEM[1:0]
DAC de-emphasis control
0
MUT
DAC Lch and Rch soft mute control
Register 3
15–11
res
Reserved, should be set to 0
10–9
A[1:0]
Register address 11
8–6
res
Reserved, should be set to 0
5
LOP
ADC/DAC analog loopback control
4–2
FMT[2:0]
ADC/DAC audio data format selection
1
LRP
ADC/DAC polarity of LR-clock selection
0
res
Reserved, should be set to 0
PROGRAM REGISTER 0
res:
Bits 15:11 – Reserved
These bits are reserved and should be set to 0.
A[1:0]:
Bits 10:9 – Register Address
These bits definte the address for REGISTER 0:
A1
A0
0
0
Register 0
LDL:
Bit 8 – DAC Attenuation Data Load Control for Left Channel
This bit is used to simultaneously set the analog outputs of the left and right channels. The output
level is controlled by AL[7:0] attenuation data when this bit is set to 1. When set to 0, the new
attenuation data is stored into a register, and the output level remains at the previous attenuation
level. The LDR bit in REGISTER 1 has the equivalent function as LDL. When either LDL or LDR is
set to 1, the output levels of the left and right channels are simultaneously controlled.
28



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