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AM53C94JC Datasheet(PDF) 24 Page - Advanced Micro Devices

Part # AM53C94JC
Description  High Performance SCSI Controller
PDF  63 Pages
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Manufacturer  AMD [Advanced Micro Devices]
Direct Link  http://www.amd.com
Logo AMD - Advanced Micro Devices

AM53C94JC Datasheet(HTML) 24 Page - Advanced Micro Devices

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P R E L I M I N A R Y
AMD
24
Am53C94/Am53C96
Target Selected without ATN Steps
Internal State
Interrupt Status
Register (06H)
Register (05H)
Explanation
Bits 2:0 (Hex)
Bits 7:0 (Hex)
2
11
Selected; received entire CDB; check group code valid bit; initiator asserted ATN
in command phase
1
11
Sequence halted in command phase due to parity error; some CDB bytes may
not have been received; check FIFO flags; initiator asserted ATN in command
phase
2
01
Selected; received entire CDB; check group code valid bit
1
01
Sequence halted in command phase because of parity error; some CDB bytes
may not have been received; check FIFO flags
0
01
Selected; loaded bus ID into FIFO; null–byte message loaded into FIFO
Target Select with ATN Steps, SCSI–2 Bit NOT SET
Internal State
Interrupt Status
Register (06H)
Register (05H)
Explanation
Bits 2:0 (Hex)
Bits 7:0 (Hex)
2
12
Selection complete; received one message byte and entire CDB; initiator as-
serted ATN during command phase
1
12
Halted in command phase; parity error and ATN true
0
12
Selected with ATN; stored bus ID and one message byte; sequence halted be-
cause ATN remained true after first message byte
2
02
Selection completed; received one message byte and the entire CDB
1
02
Sequence halted in command phase because of parity error; some CDB bytes
not received; check group code valid bit and FIFO flags
0
02
Selected with ATN; stored bus ID and one message byte; sequence halted be-
cause of parity error or invalid ID message
Target Select with ATN Steps, SCSI–2 Bit SET
Internal State
Interrupt Status
Register (06H)
Register (05H)
Explanation
Bits 2:0 (Hex)
Bits 7:0 (Hex)
5
12
Halted in command phase; parity error and ATN true
4
12
ATN remained true after third message byte
0
02
Selected with ATN; stored bus ID and one message byte; sequence halted be-
cause of parity error or invalid ID message
6
02
Selection completed; received three message bytes and the entire CDB
5
02
Received three message bytes then halted in command phase because of parity
error; some CDB bytes not received; check group code valid bit and FIFO flags
402Parity error during second or third message byte
Target Receive Command Steps
Internal State
Interrupt Status
Register (06H)
Register (05H)
Explanation
Bits 2:0 (Hex)
Bits 7:0 (Hex)
2
18
Received entire CDB; initiator asserted ATN
1
18
Sequence halted during command transfer due to parity error; ATN asserted by
initiator
2
08
Received entire CDB
1
08
Sequence halted during command transfer due to parity error; check FIFO flags
Target Disconnect Steps
Internal State
Interrupt Status
Register (06H)
Register (05H)
Explanation
Bits 2:0 (Hex)
Bits 7:0 (Hex)
2
28
Disconnect steps fully executed; disconnected; bus is free
1
18
Two message bytes sent; sequence halted because initiator asserted ATN
0
18
One message byte sent; sequence halted because initiator asserted ATN



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