ZSSC3230 Datasheet

R36DS0062ED0100 1.4

Jun 10, 2025

Page 23

© 2025 Renesas Electronics

6.6.3 EOC and Output Interrupt Signaling

The EOC pin can be programmed to operate either as a

“measurement busy” indicator and end-of-conversion (EOC)

transducer, or as a configurable interrupt transducer. The respective basic operation must be programmed into INT_setup

bits in the memory (bits[8:7] in NVM register 02HEX; see Table 16). One or two 24-bit-quantized thresholds can be

programmed (see the Interrupt Level Setup memory registers: 13HEX, 14HEX and 15HEX). Depending on the INT_setup

selection, the EOC pin provides a logic 1 or logic 0 according to the SSC-corrected measurement result. The respective

thresholds are programmed left-aligned in the memory, such that they must be

programmed with the threshold’s MSB in

the memory register’s MSB, etc. The LSBs of the 24-bit threshold in the memory must be ignored according to the number

of bits of the selected ADC resolution (according to adc_bits).

If only the effective end-of-conversion is signaled (INT_setup = 00BIN), the EOC signal is pulled LOW for the duration of the

configured conversion time. After the conversion is complete, the EOC signal is released and returns to HIGH.

The interrupt functionality is only available for digital values from the SSC-calculation unit. The interrupt feature cannot

monitor any type of raw values. The encoding and data format of the interrupt thresholds is the same as for SSC-corrected

measurement results (see Table 12).

Table 12. Data Format of Interrupt Thresholds (TRSH1 and TRSH2)

Bit-Number:

23

22

21

20

…

2

1

0

Meaning, Weighting:

20

2-1

2-2

2-3

…

2-21

2-22

2-23