©2005 Silicon Image, Inc. All rights reserved. Silicon Image, the Silicon Image logo, SiI, SiI9002, PanelLink, the PanelLink logo

and TMDS are trademarks or registered trademarks of Silicon Image, Inc. in the United States and other countries. Other

trademarks are the property of their respective holders. Product specifications are subject to change without notice.

Printed in the U.S.A. 11/05

SiI PB-0066

Silicon Image, Inc.

1060 E. Arques, Sunnyvale, CA 94085

T 408.616.4000

F 408.830.9530

www.siliconimage.com

Si

I

9002

HDMI Transmitter PHY

Features

HDMI Data Input

• 12-bit bus using a dual-edge clock

• Selectable primary edge for input data

using the edge bit

• De-skewing option to adjust data setup

and hold time

• Configurable by pin settings or

PanelLink TMDS

Digital Core

• Video information encoded onto three

TMDS differential data lines

• Adjustable TMDS low-voltage swing

amplitude for long cable support

• 1.65 Gb/s per data channel

• Running at 50KHz for host communication

• Data Latched in 12-bit mode

Hot Plug Detection Mode

• A connected display is automatically detected

using the hot plug signal for reliable TV

reconnection

Dual Zone PLL

• Dual-zone PLL changes its operational

parameters depending on the frequency

zone selected

• Operating zone optimization contributes

to robust operation over long cables

Power Management

• 3.3 V core provides low-power operation

• Low-power standby mode

Starter Kits

Reference designs for SiI 9002 with integrated

digital Transmitter IP will be provided by

Silicon Image’s licensed SoC partners.

Please visit www.siliconimage.com for partner

information.

Part Number - 9002CSU

SiI 9002

Flash

TMDS Data

IDCK

TMDS Clock

Q[0:11]

DRAM

SPDIF

HDMI

Connector

Component

Video

Y/C

CVBS

R

L

(e.g. CS4434)

HDMI

Digital

Logic IP

DVD/STB

MPEG

Processor

System on Chip

Application Block Diagram:

Example System with SiI 9002

Reference design supplied by MPEG silicon manufacturer,

in partnership with Silicon Image