www.ti.com

FEATURES

D, DGV, NS, OR PW PACKAGE

(TOP VIEW)

1

2

3

4

5

6

7

14

13

12

11

10

9

8

1A

1B

2A

2B

2C

2Y

GND

VCC

1C

1Y

3C

3B

3A

3Y

DESCRIPTION/ORDERING INFORMATION

Y

A

B

C

SN74ALVC10

TRIPLE 3-INPUT POSITIVE-NAND GATE

SCES106H – JULY 1997 – REVISED OCTOBER 2004

•

Operates From 1.65 V to 3.6 V

•

Max tpd of 3 ns at 3.3 V

•

±24-mA Output Drive at 3.3 V

•

Latch-Up Performance Exceeds 250 mA Per

JESD 17

•

ESD Protection Exceeds JESD 22

– 2000-V Human-Body Model (A114-A)

– 200-V Machine Model (A115-A)

– 1000-V Charged-Device Model (C101)

This triple 3-input positive-NAND gate is designed for 1.65-V to 3.6-V VCC operation.

The SN74ALVC10 performs the Boolean function Y = A

• B • C or Y = A + B + C in positive logic.

ORDERING INFORMATION

TA

PACKAGE(1)

ORDERABLE PART NUMBER

TOP-SIDE MARKING

Tube

SN74ALVC10D

SOIC - D

ALVC10

Tape and reel

SN74ALVC10DR

-40

°C to 85°C

SOP - NS

Tape and reel

SN74ALVC10NSR

ALVC10

TSSOP - PW

Tape and reel

SN74ALVC10PWR

VA10

TVSOP - DGV

Tape and reel

SN74ALVC10DGVR

VA10

(1)

Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at

www.ti.com/sc/package.

FUNCTION TABLE

(each gate)

INPUTS

OUTPUT

Y

A

B

C

H

H

H

L

L

X

X

H

X

L

X

H

X

X

L

H

LOGIC DIAGRAM, EACH GATE (POSITIVE LOGIC)

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Copyright © 1997–2004, Texas Instruments Incorporated

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.