THS10064CDAR datasheet(29/44 Pages) TI2

29 / 44 page

THS10064

SLAS255B – DECEMBER 1999 – REVISED DECEMBER 2002

www.ti.com

Read Timing Parameter (CS0-controlled)†

PARAMETER

MIN

TYP

MAX

UNIT

tsu(R/W)

Setup time, R/W high to last CS valid

Access time, last CS valid to data valid

td(CSDAV) Delay time, last CS valid to DATA_AV inactive

Hold time, first CS invalid to data invalid

th(R/W)

Hold time, first external CS invalid to R/W change

tw(CS)

Pulse duration, CS active

† CS = CS0

Write Timing (using R/W, CS0-controlled)

Figure 39 shows the write-timing behavior when the WR(R/W) input is programmed as a combined read-write input

R/W. The RD input has to be tied to high-level in this configuration. This timing is called CS0-controlled because CS0

is the last external signal of CS0, CS1, and R/W which becomes valid.

90%

10%

tw(CS)

tsu(R/W)

th(R/W)

CS0

CS1

D(0–9)

DATA_AV

10%

tsu

Figure 39. Write Timing Diagram Using R/W (CS0-controlled)

Read Timing Parameter (CS0-controlled)†

PARAMETER

MIN

TYP

MAX

UNIT

tsu(R/W)

Setup time, R/W stable to last CS valid

tsu

Setup time, data valid to first CS invalid

Hold time, first CS invalid to data invalid

th(R/W)

Hold time, first CS invalid to R/W change

tw(CS)

Pulse duration, CS active

† CS = CS0

THS10064CDAR Datasheet(PDF) 29 Page - Texas Instruments

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