TLC5905

LED DRIVER

SLLS401 – NOVEMBER 1999

6

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

Terminal Functions

TERMINAL

I/O

DESCRIPTION

NAME

NO.

I/O

DESCRIPTION

BCENA

55

I

Brightness control enable. When BCENA is low, the brightness control latch is set to the

default value. The output current value in this status is 100% of the value set by an external

resistor. The frequency division ratio of GSCLK is1/1. When BCENA is high, writing to

brightness control latch is enabled.

BLANK

45

I

Blank(Light off). When BLANK is high, all the output of the constant current driver is turned

off. The constant current output is turned on (LED on) when synchronized to the falling edge

of GCLK after next rising edge of GCLK when BLANK goes from high to low.

BOUT

34

O

Blank signal delay. BOUT is an output with the addition of delay time to BLANK.

GSCLK

46

I

Clock input for gray scale. The gray scale display is accomplished by lighting the LED on until

the number of GSCLK counted is equal to data latched.

GNDANA

28

Analog ground (internally connected to GNDLOG and GNDLED)

GNDLED

3,6,11,14,

19,22,59,62

LED driver ground (internally connected to GNDANA and GNDLOG)

GNDLOG

54

Logic ground (internally connected to GNDANA and GNDLED)

GSOUT

33

O

Clock delay for gray scale. GSOUT is an output with the addition of delay time to GSCLK.

IREF

25

I/O

Constant current value setting. LED current is set to the desired value by connecting an

external resistor between IREF and GND. The 37 times current is compared to current across

the external resistor sink on the output terminal.

MCENA

31

I

OVM enable. When MCENA is low, the OVM latch is set to the default value. The comparison

voltage in this status is 0.3 V. When MCENA is high, writing to OVM latch is enabled.

MODE

53

I

8/16 bits select. When MODE is high, the 16 bits output is selected. When MODE is low, the

8 bits output is selected.

NC

1,7,10,16,17,24,

29,50,56,57,64

No internal connection

OUT0 – OUT15

58,60,61,63,

2,4,5,8,9,12,13

15,18,20,21,23

O

Constant current output

RSEL0

RSEL1

43

44

I

Shift register data latch switching.

When RSEL1 is low and RESL0 is low, gray scale data shift register latch is selected.

When RSEL1 is low and RESL0 is high, the brightness control register latch is selected.

When RSEL1 is high and RSEL0 is low, the OVM register latch is selected.

When RSEL1 is high and RSEL0 high, no register latch is selected.

SCLK

42

I

Clock input for data transfer. The input data is from SIN. All data on the shift register selected

by RSEL0 and RSEL1, and output data at SOUT are sifted by 1 bit synchronizing to SCLK.

The data except the SOUT is synchronized to the rising edge. The edge for data from SOUT

is determined by the level of SOMODE.

SIN

49

I

Input for 1 bit serial data. These terminals are inputs for shift register for gray scale data,

brightness control and OVM. The register selected is determined by RSEL0, 1.

SOMODE

47

I

Timing select for data output. When SOMODE is low, SOUT is changed by synchronizing to

the rising edge of SCLK. When SOMODE is high, SOUT is changed by synchronizing to the

falling edge of SCLK.

SOUT

32

O

Output for 1 bit serial data with 3–state. These terminals are outputs for shift register for gray

scale data, brightness control and OVM. The register selected is determined by RSEL0, 1.

TEST1

TEST2

35

48

I

TEST. Factory test terminal. TEST1 and TEST2 should be connected to GND for normal

operation.

THERMAL PAD

package bottom

Heat sink pad. This pad is connected to the lowest potential IC or thermal layer.

TSENA

51

I

TSD (thermal shutdown) enable. When TSENA is high, TSD is enabled. When TSENA is low,

TSD is disabled.