TLV571

2.7 V TO 5.5 V, 1-CHANNEL, 8-BIT,

PARALLEL ANALOG-TO-DIGITAL CONVERTER

SLAS239A – SEPTEMBER 1999 – REVISED FEBRUARY 2000

12

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

software START conversion (continued)

system clock source

The TLV571 internally derives multiple clocks from the SYSCLK for different tasks. SYSCLK is used for most

conversion subtasks. The source of SYSCLK is programmable via control register zero, bit 3. The source of

SYSCLK is changed at the rising edge of WR of the cycle when CR0.D3 is programmed.

internal clock (CR0.D3 = 0, SYSCLK = internal OSC)

The TLV571 has a built-in 10 MHz OSC. When the internal OSC is selected as the source of SYSCLK, the

internal clock starts with a delay (one half of the OSC period max) after the falling edge of the conversion trigger

(either WR, RD, or CSTART). The OSC speed can be set to 10

± 1 MHz or 20 ± 2 MHz by setting register bit

CR1.D4.

external clock (CR0.D3 = 1, SYSCLK = external clock)

The TLV571 is designed to accept an external clock input (CMOS/TTL logic) with frequencies from 1 MHz to

20 MHz.

host processor interface

The TLV571 provides a generic high-speed parallel interface that is compatible with high-performance DSPs

and general-purpose microprocessors. The interface includes D(0–7), INT/EOC, RD, and WR.

output format

The data output format is unipolar (code 0 to 255). The output code format can be either binary or twos

complement by setting register bit CR1.D1.

power up and initialization

After power up, CS must be low to begin an I/O cycle. INT/EOC is initially high. The TLV571 requires two write

cycles to configure the two control registers. The first conversion after the device has returned from the power

down state may be invalid and should be disregarded.

definitions of specifications and terminology

integral nonlinearity

Integral nonlinearity refers to the deviation of each individual code from a line drawn from zero through full scale.

The point used as zero occurs 1/2 LSB before the first code transition. The full-scale point is defined as level

1/2 LSB beyond the last code transition. The deviation is measured from the center of each particular code to

the true straight line between these two points.

differential nonlinearity

An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal value.

A differential nonlinearity error of less than

±1 LSB ensures no missing codes.

zero offset

The major carry transition should occur when the analog input is at zero volts. Zero error is defined as the

deviation of the actual transition from that point.

gain error

The first code transition should occur at an analog value 1/2 LSB above negative full scale. The last transition

should occur at an analog value 1 1/2 LSB below the nominal full scale. Gain error is the deviation of the actual

difference between first and last code transitions and the ideal difference between first and last code transitions.