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TLV7021 Datasheet(PDF) 12 Page - Texas Instruments |
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TLV7021 Datasheet(HTML) 12 Page - Texas Instruments |
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12 / 22 page ![]() IN - V± V+ + OUT Micro- Controller UV VDD VPULL-UP REF 1.7 to 5.5 V TLV7081 Battery Copyright © 2017, Texas Instruments Incorporated 12 TLV7081 SNOSD69A – MAY 2018 – REVISED JUNE 2018 www.ti.com Product Folder Links: TLV7081 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated 8 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 8.1 Application Information The TLV7081 is a 4-pin, nano-power comparator with open-drain output that is well suited for monitoring battery voltages. The TLV7081's benefits include a small package footprint and a unique input stage that allows the comparator input to be driven by a voltage source even when the operating voltage for the comparator is turned- off (zero volts). 8.2 Typical Applications 8.2.1 Nano-Power Battery Monitor The application of the TLV7081 for an under-voltage detection circuit is shown in Figure 21. Figure 21. Under-Voltage Detection 8.2.1.1 Design Requirements For this design, follow these design requirements: • The supply voltage connected to pin (V+) serves as the reference voltage for the comparator and can be any voltage between 1.7 V and 5.5 V. • The voltage applied to the input pin (IN) can be any voltage in the range of 0 V to 5.6 V. This voltage range is uniquely independent of the supply voltage applied to pin (V+). • The comparator output pin (OUT) requires a pull-up resistor that sets the output-high logic level (VOH) for the comparator. VPULL-UP should be connected to the supply voltage of the microcontroller which is monitoring the comparator output and serves as the level-shifting block for the logic levels in the application. |
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