Inductor Current

t

Low-side FET valley current limit

Maximum load current

Peak current at low-side

FET valley current limit

High-side FET peak current limit

9

TLV62565, TLV62566

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SLVSBC1D – OCTOBER 2013 – REVISED OCTOBER 2016

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Feature Description (continued)

9.3.2 Enabling/Disabling the Device

The TLV62565 is enabled by setting the EN input to a logic HIGH. Accordingly, a logic LOW disables the device.

If the device is enabled, the internal power stage starts switching and regulates the output voltage to the set point

voltage. The EN input must be terminated and should not be left floating.

9.3.3 Soft Start

After enabling the device, internal soft-start circuitry monotonically ramps up the output voltage which reaches

nominal output voltage during a soft-start time of 250 µs (typical). This avoids excessive inrush current and

creates a smooth output voltage rise slope. It also prevents excessive voltage drops of primary cells and

rechargeable batteries with high internal impedance.

If the output voltage is not reached within the soft-start time, such as in the case of a heavy load, the converter

enters regular operation. The TLV62565/6 are able to start into a pre-biased output capacitor. The converter

starts with the applied bias voltage and ramps the output voltage to its nominal value.

9.3.4 Switch Current Limit

The switch current limit prevents the device from high inductor current and drawing excessive current from a

battery or input voltage rail. Excessive current might occur with a heavy load or shorted output circuit condition.

The TLV62565/6 adopt valley current control by sensing the current of the low-side FET. If the inductor current

reaches the low-side FET valley current limit ILIM,LS (typical 1.7 A), the low-side FET is turned off and the high-

side FET is turned on to ramp up the inductor current. The current ramping up time is controlled by the on time

setting of the device, as shown in Figure 7. For example, the peak current is 1.97 A when the switch current limit

is triggered with 3.6 VIN to 1.8 VOUT and 2.2-μH application.

To prevent the inductor current from running away, the devices implement an additional high-side peak current

limit ILIM,HS (typical 2 A), which is shown in Figure 7. It forces to turn off the high side FET immediately once the

peak inductor current reaches the threshold. Due to the internal propagation delay, the real current limit value

might be higher than the static current limit in the electrical characteristics table.

Figure 7. Switch Current Limit

9.3.5 Power Good

The TLV62566 integrates a Power Good output going low when the output voltage is below its nominal value.

The Power Good output stays high impedance once the output is above 95% of the regulated voltage and is low

once the output voltage falls below typically 90% of the regulated voltage. The PG pin is an open drain output

and is specified to sink typically up to 0.5 mA. The Power Good output requires a pull-up resistor connected to

any voltage lower than 5.5 V. When the device is off due to UVLO or thermal shutdown, the PG pin is pulled to

logic low.

9.4 Device Functional Modes

9.4.1 Under Voltage Lockout

To avoid mis-operation of the device at low input voltages, under voltage lockout is implemented that shuts down

the device at voltages lower than VUVLO with VHYS_UVLO hysteresis.