IP1000A LF
Preliminary Data Sheet
8/75
July 5, 2005
Copyright © 2005, IC Plus Corp.
IP1000A LF-DS-R08
PIN Description (continued)
Pin no.
Label
Type
Description
PCI interface (continued)
101
IRDYN
I/O
Initiator Ready, asserted LOW.
A bus master asserts IRDYN to indicate valid data phases
on AD during write data phases, and to indicate it is ready to
accept data during read data phases. A target will monitor
IRDYN.
104
STOPN
I/O
Stop, asserted LOW.
STOPN is driven by the slave target to inform the bus
master to terminate the current transaction.
103
DEVSELN
I/O
Device Select, asserted LOW.
The IP1000A LF asserts DEVSELN when it is selected as a
target during a bus transaction. It monitors DEVSELN for
any target to acknowledge a bus transaction initiated by the
IP1000A LF.
82
IDSEL
I
Initialization Device Select.
The IDSEL is used to select the IP1000A LF during
configuration read and write transactions.
67
PCICLK
I
PCI Bus Clock.
This clock is used to drive the PCI bus interfaces and the
internal DMA logic. All bus signals are sampled on the rising
edge of PCICLK. PCICLK can operate from 0MHz to
66MHz, on a PCI bus.
105
PERRN
I/O
Parity Error, asserted LOW.
The IP1000A LF asserts PERRN when it checks and
detects a bus parity error. When it is generating PAR output,
the IP1000A LF monitors for any reported parity error on
PERRN.
107
SERRN
O
System Error, asserted LOW.
68
REQN
O
Request, asserted LOW.
The IP1000A LF asserts REQN to request PCI bus master
operation.
62
GNTN
I
PCI Bus Grant, asserted LOW.
GNTN signals access to the PCI bus has been granted to
IP1000A LF.
80, 96, 112,
125
CBE [3:0] N
I/O
PCI Bus Command/Byte Enable, asserted LOW.
Bus command and byte enables are multiplexed on the
CBEN signals. CBEN specify the bus command during the
address phase transaction, and carry byte enables during
the data phase.
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