IP1000A LF
Preliminary Data Sheet
56/75
July 5, 2005
Copyright © 2005, IC Plus Corp.
IP1000A LF-DS-R08
3.2.2.16 MemBaseAddress
Class............................. PCI Configuration Registers
I/O Base Address ......... PCI device configuration header start
Address Offset .............. 0x14
Default Value ................ 0x00000000
Access Rule.................. Double Word
Width ............................ 32 bits
MemBaseAddress can be disabled via loading of the ConfigParm field from an EEPROM during
auto-iniTialization of the IP1000A LF. When AsicCtrlRegister ForcedConfig[0] is 1, the IP1000A LF is in
ForcedConfig Mode. In this mode, the MemBase Address is loaded from EEPROM at offset 04’h(Upper
Bytes), 05’h, the same as IO BaseAddress.
Bit
BIT Name
BIT Description
Type
HW
Reset
SW
Reset
0
MemBaseAddrInd Memory
Base
Address
Indicator.
When
MemBaseAddrInd is a logic 1, MemBaseAddress
contains the valid memory base address.
R/W
2..1
MemMapType
Memory Map Type. MemMapType defines how the
host system maps the IP1000A LF’s registers within
the
host
system
memory
space.
Bit
2
of
MemMapType is always a logic 0, while bit 1 is
loaded from the Lower1Meg bit of the ConfigParm
field within an EEPROM during auto initialization of
the IP1000A LF.
BIT 2
BIT 1
REGISTER MAPPING
0
0
Anywhere
within
a
32
bit
address space
0
1
Lower 1 megabyte of 32 bit
address space
1
x
Undefined
7..3
Reserved
Reserved for future use. Write as zero, ignore on read.
N/A
31..8
MemBaseAddress Memory Base Address. MemBaseAddress contains
the 24 bit memory base address value. With 24 bits,
the IP1000A LF uses 256 bytes of I/O space.
R/W
3.2.2.17 MinGnt
Class............................. PCI Configuration Registers
I/O Base Address ......... PCI device configuration header start
Address Offset .............. 0x3E
Default Value ................ 0x50
Access Rule.................. Byte
Width ............................ 8 bits
Bit
BIT Name
BIT Description
Type
HW
Reset
SW
Reset
7..0
MinGnt
Minimum Grant Time. MinGnt specifies, in 250 ns
increments, how long a burst period the IP1000A
LF requires when operating as a bus master. Bits
7 through 4 of the MinGnt value are loaded from
the ConfigParm field within an EEPROM during
auto initialization of the IP1000A LF.
R
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