ADS1243IPWR datasheet(11/34 Pages) TI2

11 / 34 page

ADS1242, 1243

SBAS235H

www.ti.com

FIGURE 3. Burnout detection while sensor is open-circuited.

FIGURE 4. Burnout detection while sensor is short-circuited.

SPEED

DR BITS

1st NOTCH

fOSC

BIT

fMOD

FREQ.

2.4576MHz

19,200Hz

15Hz

7.5Hz

3.75Hz

50/60Hz

9,600Hz

7.5Hz

3.75Hz 1.875Hz

25/30Hz

4.9152MHz

38,400Hz

30Hz

15Hz

7.5Hz

100/120Hz

19,200Hz

15Hz

7.5Hz

3.75Hz

50/60Hz

TABLE I. Output Configuration.

OPEN CIRCUIT

µA

CODE = 0x7FFFFF

ADC

SHORT

CIRCUIT

DD/2

µA

CODE

≅ 0

ADC

shorted and at the same potential, the ADS1242/43 signal

outputs are approximately zero. (Note that the code for

shorted inputs is not exactly zero due to internal series

resistance, low-level noise and other error sources.)

INPUT BUFFER

The input impedance of the ADS1242/43 without the buffer

enabled is approximately 5M

Ω/PGA. For systems requiring

very high input impedance, the ADS1242/43 provides a

chopper-stabilized differential FET-input voltage buffer. When

activated, the buffer raises the ADS1242/43 input impedance

to approximately 5G

Ω.

The buffer’s input range is approximately 50mV to

VDD – 1.5V. The buffer’s linearity will degrade beyond this

range. Differential signals should be adjusted so that both

signals are within the buffer’s input range.

The buffer can be enabled using the BUFEN pin or the

BUFEN bit in the ACR register. The buffer is on when the

BUFEN pin is high and the BUFEN bit is set to one. If the

BUFEN pin is low, the buffer is disabled. If the BUFEN bit is

set to zero, the buffer is also disabled.

The buffer draws additional current when activated. The

current required by the buffer depends on the PGA setting.

When the PGA is set to 1, the buffer uses approximately

µA; when the PGA is set to 128, the buffer uses approxi-

mately 500

µA.

PGA

The Programmable Gain Amplifier (PGA) can be set to gains

of 1, 2, 4, 8, 16, 32, 64, or 128. Using the PGA can improve the

effective resolution of the A/D converter. For instance, with a

PGA of 1 on a 5V full-scale signal, the A/D converter can

resolve down to 1

µV. With a PGA of 128 and a full-scale signal

of 39mV, the A/D converter can resolve down to 75nV. VDD

current increases with PGA settings higher than 4.

OFFSET DAC

The input to the PGA can be shifted by half the full-scale input

range of the PGA using the Offset DAC (ODAC) register. The

ODAC register is an 8-bit value; the MSB is the sign and the

seven LSBs provide the magnitude of the offset. Using the

offset DAC does not reduce the performance of the A/D

converter. For more details on the ODAC in the ADS1242/43,

please refer to TI application report SBAA077 (available

through the TI website).

MODULATOR

The modulator is a single-loop second-order system. The

modulator runs at a clock speed (fMOD) that is derived from

the external clock (fOSC). The frequency division is deter-

mined by the SPEED bit in the SETUP register, as shown in

Table I.

CALIBRATION

The offset and gain errors can be minimized with calibration.

The ADS1242 and ADS1243 support both self and system

calibration.

Self-calibration of the ADS1242 and ADS1243 corrects inter-

nal offset and gain errors and is handled by three commands:

SELFCAL, SELFGAL, and SELFOCAL. The SELFCAL com-

mand performs both an offset and gain calibration. SELFGCAL

performs a gain calibration and SELFOCAL performs an

offset calibration, each of which takes two tDATA periods to

complete. During self-calibration, the ADC inputs are discon-

nected internally from the input pins. The PGA must be set to

1 prior to issuing a SELFCAL or SELFGCAL command. Any

PGA is allowed when issuing a SELFOCAL command. For

ADS1243IPWR Datasheet(PDF) 11 Page - Texas Instruments

ADS1243IPWR Datasheet(HTML) 11 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34

Datasheet Download

Link URL