ADS8345

SBAS177C

2

www.ti.com

ABSOLUTE MAXIMUM RATINGS(1)

+VCC to GND ........................................................................ –0.3V to +6V

Analog Inputs to GND .......................................... –0.3V to (+VCC) + 0.3V

Digital Inputs to GND ........................................................... –0.3V to +6V

Power Dissipation .......................................................................... 250mW

Maximum Junction Temperature ................................................... +150

°C

Operating Temperature Range ........................................ –40

°C to +85°C

Storage Temperature Range ......................................... –65

°C to +150°C

Lead Temperature (soldering, 10s) ............................................... +300

°C

NOTE: (1) Stresses above those listed under “Absolute Maximum Ratings”

may cause permanent damage to the device. Exposure to absolute maximum

conditions for extended periods may affect device reliability.

PIN CONFIGURATION

Top View

SSOP

PIN DESCRIPTIONS

PIN

NAME

DESCRIPTION

1

CH0

Analog Input Channel 0

2

CH1

Analog Input Channel 1

3

CH2

Analog Input Channel 2

4

CH3

Analog Input Channel 3

5

CH4

Analog Input Channel 4

6

CH5

Analog Input Channel 5

7

CH6

Analog Input Channel 6

8

CH7

Analog Input Channel 7

9

COM

Common reference for analog inputs. This pin is typically

connected to VREF.

10

SHDN

Shutdown. When LOW, the device enters a very

low-power shutdown mode.

11

VREF

Voltage Reference Input. See the Electrical Character-

istics Table for ranges.

12

+VCC

Power Supply, 2.7V to 5.25V

13

GND

Ground

14

GND

Ground

15

DOUT

Serial Data Output. Data is shifted on the falling edge of

DCLK. This output is high impedance when CS is HIGH.

16

BUSY

Busy Output. Busy goes LOW when the DIN control bits

are being read and also when the device is converting.

The Output is high impedance when CS is HIGH.

17

DIN

Serial Data Input. If CS is LOW, data is latched on rising

edge of DCLK.

18

CS

Chip Select Input; Active LOW. Data will not be clocked

into DIN unless CS is LOW. When CS is HIGH, DOUT is

high impedance.

19

DCLK

External Clock Input. The clock speed determines the

conversion rate by the equation fDCLK = 24 • fSAMPLE.

20

+VCC

Power Supply

1

2

3

4

5

6

7

8

9

10

CH0

CH1

CH2

CH3

CH4

CH5

CH6

CH7

COM

SHDN

+V

CC

DCLK

CS

D

IN

BUSY

D

OUT

GND

GND

+V

CC

V

REF

20

19

18

17

16

15

14

13

12

11

ADS8345

ELECTROSTATIC

DISCHARGE SENSITIVITY

This integrated circuit can be damaged by ESD. Texas Instru-

ments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling

and installation procedures can cause damage.

ESD damage can range from subtle performance degrada-

tion to complete device failure. Precision integrated circuits

may be more susceptible to damage because very small

parametric changes could cause the device not to meet its

published specifications.

PACKAGE/ORDERING INFORMATION

MAXIMUM

INTEGRAL

MAXIMUM

SPECIFIED

LINEARITY

GAIN

PACKAGE

TEMPERATURE

ORDERING

TRANSPORT

PRODUCT

ERROR (LSB)

ERROR (%)

PACKAGE-LEAD

DESIGNATOR(1)

RANGE

NUMBER

MEDIA, QUANTITY

ADS8345E

8

±0.05

QSOP-20

DBQ

–40

°C to +85°C

ADS8345E

Rails, 100

""

"

"

"

"

ADS8345E/2K5

Tape and Reel, 2500

ADS8345N

8

±0.05

SSOP-20

DB

–40

°C to +85°C

ADS8345N

Rails, 100

""

"

"

"

"

ADS8345N/1K

Tape and Reel, 1000

ADS8345EB

6

±0.024

QSOP-20

DBQ

–40

°C to +85°C

ADS8345EB

Rails, 100

""

"

"

"

"

ADS8345EB/2K5

Tape and Reel, 2500

ADS8345NB

6

±0.024

SSOP-20

DB

–40

°C to +85°C

ADS8345NB

Rails, 100

""

"

"

"

"

ADS8345NB/1K

Tape and Reel, 1000

NOTE: (1) For the most current specifications and package information, refer to our web site at www.ti.com.